XRT72L56 Datasheet, PDF (238/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17)
BIT 7
Not Used
BIT 6
Not Used
BIT 5
Not Used
BIT 4
FEAC
Valid
RO
RO
RO
RO
X
X
X
1
The bit-format of the Rx DS3 FEAC register is pre-
sented below. It is important to note that the last vali-
BIT 3
BIT2
BIT 1
BIT 0
RxFEAC
Remove
Interrupt
Enable
R/W
X
RxFEAC
Remove
Interrupt
status
RUR
0
RxFEAC
Valid
Interrupt
Enable
R/W
1
RxFEAC
Valid
Interrupt
Status
RUR
1
dated FEAC code word will be written into the shaded
bit-fields below.
RX DS3 FEAC REGISTER (ADDRESS = 0X16)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Not Used
RO
0
RxFEAC [5]
RO
d5
RxFEAC [4]
RO
d4
RxFEAC [3]
RO
d3
RxFEAC [2]
RO
d2
RxFEAC [1]
RO
d1
RxFEAC [0]
RO
d0
Not Used
RO
0
The purpose of generating an interrupt to the µP, up-
on FEAC Code Word Validation is to inform the local
µP that the Framer has a newly received FEAC mes-
sage that needs to be read. The local µP would read-
in this FEAC code word from the Rx DS3 FEAC Reg-
ister (Address = 0x16).
FEAC Code Removal
After the 10th transmission of a given FEAC code
word, the remote terminal equipment may proceed to
transmit a different FEAC code word. When the Re-
ceive FEAC processor detects this occurrence, it
must Remove the FEAC codeword that is presently
residing in the Rx DS3 FEAC Register. The Receive
FEAC Processor will remove the existing FEAC code
word when it detects that 3 (or more) out of the last
10 received FEAC codes are different from the latest
validated FEAC code word. The Receive FEAC Pro-
cessor will inform the local µP/µC of this removal
event by generating a Rx FEAC Removal interrupt,
and asserting the RxFEAC Remove Interrupt Status
bit in the Rx DS3 Interrupt Enable/Status Register, as
depicted below.
RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17)
BIT 7
Not Used
BIT 6
Not Used
BIT 5
Not Used
BIT 4
FEAC
Valid
RO
RO
RO
RO
X
X
X
0
Additionally, the Receive FEAC processor will also
denote the removal event by setting the FEAC Valid
bit-field (Bit 4), within the Rx DS3 FEAC Interrupt En-
able/Status Register to 0, as depicted above.
BIT 3
BIT2
BIT 1
BIT 0
RxFEAC
Remove
Interrupt
Enable
R/W
1
RxFEAC
Remove
Interrupt
status
RUR
1
RxFEAC
Valid
Interrupt
Enable
R/W
X
RxFEAC
Valid
Interrupt
Status
RUR
0
The description of Bits 0 through 3 within this register,
all support Interrupt Processing, and will therefore be
presented in Section 3.3.6. Figure 84 presents a flow
diagram depicting how the Receive FEAC Processor
functions.
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