XRT72L56 Datasheet, PDF (116/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
NOTE: For more information on the LOF Condition, please
see Section 4.3.2.2.
Bit 1 - LOS (Change in LOS Condition) Interrupt
Enable
This Read/Write bit-field allows the user to enable or
disable the Change in LOS condition interrupt. Set-
ting this bit-field to "1" enables this interrupt. Setting
this bit-field to "0" disables this interrupt.
NOTE: For more information on the LOS Condition, please
see Section 4.3.2.7.
Bit 0 - AIS (Change in AIS Condition) Interrupt En-
able
This Read/Write bit-field allows the user to enable or
disable the Change in AIS condition interrupt. Setting
this bit-field to "1" enables this interrupt. Setting this
bit-field to "0" disables this interrupt.
NOTE: For more information on the AIS Condition, please
see Section 4.3.2.8
2.4.4.4 Receive E3 Interrupt Enable Register -
2 (E3, ITU-T G.751)
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Not Used
FERF
Interrupt
Enable
R/W
RO
RO
RO
R/W
0
0
0
0
0
BIT 2
BIT 1
BIP-4 Error Framing Error
Interrupt
Interrupt
Enable
Enable
R/W
R/W
0
0
BIT 0
Not Used
RO
0
Bit 3 - FERF (Far-End Receive Failure) Interrupt
Enable
This Read/Write bit-field allows the user to enable or
disable the Change in FERF Condition interrupt. Set-
ting this bit-field to "1" enables this interrupt. Setting
this bit-field to "0" disables this interrupt.
NOTE: For more information on the Change in FERF Condi-
tion interrupt, please see Section 4.3.6.1.6.
Bit 2 - BIP-4 Error Interrupt Enable
This Read/Write bit-field allows the user to enable or
disable the BIP-4 Error interrupt. Setting this bit-field
to "1" enables this interrupt. Setting this bit-field to
"0" disables this interrupt.
NOTE: For more information on this interrupt, please see
Section 4.3.6.1.7.
Bit 1 - Framing Error Interrupt Enable
This Read/Write bit-field allows the user to enable or
disable the Framing Error interrupt. Setting this bit-
field to "1" enables this interrupt. Setting this bit-field
to "0" disables this interrupt.
NOTE: For more information on this interrupt, please see
Section 4.3.6.1.8.
2.4.4.5 Receive E3 Interrupt Status Register -
1 (E3, ITU-T G.751)
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
COFA
Interrupt
Status
OOF
Interrupt
Status
LOF
Interrupt
Status
LOS
Interrupt
Status
AIS
Interrupt
Status
R/W
RO
RO
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Bit 4 - COFA (Change of Framing Alignment) In-
terrupt Status
This Reset-upon-Read bit-field will be set to "1" if the
Change of Frame Alignment interrupt has occurred
since the last read of this register.
The Receive E3 Framer will generate the Change of
Frame Alignment interrupt if it has detected a change
in frame alignment in the incoming E3 frames.
Bit 3 - OOF (Change in OOF Condition) Interrupt
Status
This Reset Upon Read bit-field is set to "1" if the Re-
ceive DS3/E3 Framer block has detected a Change in
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