XRT72L56 Datasheet, PDF (76/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
illustrate how this burst access operation works, the
byte (or word) of data, that is being read in Figure 29,
has been labeled Valid Data at Offset = 0x00. This
label indicates that the µC/µP is reading the very first
register (or buffer location) in this burst access opera-
tion.
2.3.2.2.1.1.2 The Subsequent Read Operations
The procedure that the µC/µP must use to perform
the remaining read cycles, within this Burst Access
operation, is presented below.
B.0 Execute each subsequent Read Cycles, as
described in steps 1 through 3 below.
B.1 Without toggling the ALE_AS input pin (e.g.,
keeping it "Low"), toggle the RD_DS input pin
"Low". This step accomplishes the following.
a. The Framer will internally increments the latched
address value (within the Microprocessor Inter-
face circuitry).
b. The output drivers of the bi-directional data bus,
D[7:0] are enabled. At some time later, the regis-
ter or buffer location corresponding to the incre-
mented latched address value will be driven onto
the bi-directional data bus.
B.2 Immediately after the Read Strobe pin toggles
"Low" the Framer IC will toggle the RDY_DTCK
(READY) output pin "Low" to indicate its NOT
READY status.
B.3 After some settling time, the data on the bi-
directional data bus will stabilize and can be
read by the µC/µP. The XRT72L56 DS3/E3
Framer will indicate that this data is ready to be
read by toggling the RDY_DTCK (READY) sig-
nal "High".
B.4 After the µC/µP detects the RDY_DTCK signal
(from the XRT72L56 DS3/E3 Framer), it can
then terminates the Read cycle by toggling the
RD_DS (Read Strobe) input pin "High".
For subsequent read operations, within this burst cy-
cle, the µC/µP simply repeats steps 1 through 3, as il-
lustrated in Figure 30.
FIGURE 30. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING SUBSEQUENT READ OPERATIONS
WITHIN THE BURST I/O CYCLE
ALE_AS
A(11:0)
Address of "Initial" Target Register (Offset = 0x00)
CS
D(7:0)
RD_DS
Not Valid
Valid Data at
Offset = 0x01
Not Valid
Valid Data at
Offset = 0x02
WR_R/W
RDY_DTCK
In addition to the behavior of the Microprocessor In-
terface signals, Figure 30 also illustrates other points
regarding the Burst Access Operation.
a. The Framer internally increments the address
value, from the original latched value shown in
Figure 29. This is illustrated by the data, appear-
ing on the data bus, (for the first read access)
being labeled Valid Data at Offset = 0x01 and that
for the second read access being labeled Valid
Data at Offset = 0x02.
b. The Framer performs this address incrementing
process even though there are no changes in the
Address Bus Data, A[11:0].
2.3.2.2.1.1.3 Terminating the Burst Access
Operation
The Burst Access Operation will be terminated upon
the rising edge of the ALE_AS input signal. At this
point the Framer will cease to internally increment the
latched address value. Further, the µC/µP is now free
to execute either a Programmed I/O access or to start
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