XRT72L56 Datasheet, PDF (113/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
This Read-Only register contains the fourteenth
(14th) byte within the 16 byte Trail Trace Buffer Mes-
sage, that has been received from the Remote Termi-
nal. This register typical contains an ASCII character
that is required for the E.164 numbering format.
NOTE: For more information on the use of this register,
please see Section 5.3.2.9.
2.4.3.25 Receive E3 TTB-14 Register (E3, ITU-T
G.832)
RXE3 TTB-14 REGISTER (ADDRESS = 0X2A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxTTB-14
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
This Read-Only register contains the fifteenth (15th)
byte within the 16 byte Trail Trace Buffer Message,
that has been received from the Remote Terminal.
This register typical contains an ASCII character that
is required for the E.164 numbering format.
NOTE: For more information on the use of this register,
please see Section 5.3.2.9.
2.4.3.26 Receive E3 TTB-15 Register (E3, ITU-T
G.832)
RXE3 TTB-15 REGISTER (ADDRESS = 0X2B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxTTB-15
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
This Read-Only register contains the sixteenth (16th)
byte within the 16 byte Trail Trace Buffer Message,
that has been received from the Remote Terminal.
This register typical contains an ASCII character that
is required for the E.164 numbering format.
RXE3 SSM REGISTER (ADDRESS = 0X2B)
BIT 7
RxSSM
Enable
BIT 6
BIT 5
MFI[1:0]
BIT 4
Reserved
R/W
RO
RO
RO
0
0
0
0
NOTE: For more information on the use of this register,
please see Section 5.3.2.9.
2.4.3.27 Receive E3 Framer SSM Register
BIT 3
RO
0
BIT 2
BIT 1
RxSSM[3:0]
RO
RO
0
0
BIT 0
RO
0
Bit 7 - RxSSM Enable
This Read/Write bit-field permits the user to configure
the Receive Section of a given channel to support
processing of the MA byte via either the “old” or the
“new” ITU-T G.832 Framing format.
Setting this bit-field to “1” configures the Receive
Section to support the “new” E3, ITU-T G.832 framing
standard (October 1998 Revision). Setting this bit-
field to “0” configures the Receive Section to support
the “old” E3, ITU-T G.832 framing standard (Novem-
ber 1995).
Bits 6, 5 - MF[1:0] - SSM Multiframe Indicator Bits
These two bits reflect the states of the SSM Multi-
frame phase indicators, within the most recently re-
ceived E3 frame. Stated another ways, these two bit-
fields reflect Bits 2 and 1 within the MA byte, in the
most recently received E3 frame.
NOTE: These two bit-fields are only valid if the Receive
Section of the Channel has been configured to support the
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