XRT72L56 Datasheet, PDF (278/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
FIGURE 101. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT72L56 TRANSMIT PAYLOAD
DATA INPUT INTERFACE BLOCK AND THE TERMINAL EQUIPMENT (FOR MODE 1 OPERATION)
Terminal Equipment Signals
E3_Clock_In
E3_Data_Out
Tx_Start_of_Frame
E3_Overhead_Ind
Payload[1522] Payload[1523]
FAS, Bit 9
FAS, Bit 8
XRT72L5x Transmit Payload Data I/F Signals
RxOutClk
TxSer
Payload[1522] Payload[1523]
TxFrame
TxOH_Ind
FAS, Bit 9
FAS, Bit 8
E3 Frame Number N
Note: TxFrame pulses high to denote
E3 Frame Boundary.
Note: TxOH_Ind pulses high for
12 bit periods in order to
denote Overhead Data
(e.g., the FAS pattern and the
A & N bits).
E3 Frame Number N + 1
Note: The FAS pattern will not be processed by the
Transmit Payload Data Input Interface.
How to configure the XRT72L56 into the Serial/
Loop-Timed/Non-Overhead Interface Mode
1. Set the NibIntf input pin "Low".
2. Set the TimRefSel[1:0] bit fields (within the
Framer Operating Mode Register) to "00", as
illustrated below.
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Local
Loopback
DS3/E3*
Internal
LOS
Enable
RESET
R/W
R/W
R/W
R/W
0
0
1
0
3. Interface the XRT72L56, to the Terminal Equip-
ment, as illustrated in Figure 100.
5.2.1.2 Mode 2 - The Serial/Local-Timed/
Frame-Slave Mode Behavior of the XRT72L56
If the XRT72L56 has been configured to operate in
this mode, then the XRT72L56 will function as fol-
lows.
A. Local-Timed - Uses the TxInClk signal as the
Timing Reference
Interrupt
Enable
Reset
Frame
Format
TimRefSel[1:0]
R/W
R/W
R/W
R/W
1
0
0
0
In this mode, the Transmit Section of the XRT72L56
will use the TxInClk signal as its timing reference.
B. Serial Mode
The XRT72L56 will receive the E3 payload data, in a
serial manner, via the TxSer input pin. The Transmit
Payload Data Input Interface (within the XRT72L56)
will latch this data into its circuitry, on the rising edge
of the TxInClk input clock signal.
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