XRT72L56 Datasheet, PDF (365/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
the RxE3 Interrupt Enable Register - 2, as indicated
below.
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Not Used
FERF
Interrupt
Enable
R/W
RO
RO
RO
R/W
0
0
0
0
0
BIT 2
BIT 1
BIP-4 Error Framing Error
Interrupt
Interrupt
Enable
Enable
R/W
R/W
0
0
BIT 0
Not Used
RO
0
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Servicing the Change in Receive FERF Condition
Interrupt
Whenever the XRT72L56 Framer IC detects this in-
terrupt, it will do all of the following.
• It will assert the Interrupt Request output pin (INT),
by driving it “Low”.
• It will set Bit 3 (FERF Interrupt Status), within the
Rx E3 Interrupt Status Register - 2 to “1”, as indi-
cated below.
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
FERF
Interrupt
Status
BIP-4
Error
Interrupt
Status
Framing
Error
Interrupt
Status
Not Used
RO
RO
RO
RO
RUR
RUR
RUR
RUR
0
0
0
0
1
0
0
0
Whenever the user’s system encounters the Change
in Receive FERF Condition Interrupt, then it should
do the following.
1. It should determine the current state of the FERF
condition. Recall, that this interrupt can be gen-
erated, whenever the XRT72L56 Framer IC
declares or clears the FERF defect. Hence, the
user can determine the current state of the LOS
defect by reading the state of Bit 0 (RxFERF)
within the Rx E3 Configuration and Status Regis-
ter - 2, as illustrated below.
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxLOF
Algo
RxLOF
RxOOF
RxLOS
RxAIS
Not Used
RxFERF
R/W
RO
RO
RO
RO
RO
RO
RO
0
1
1
0
0
1
1
1
5.3.6.2.7 The Detection of BIP-4 Error Interrupt
If the Detection of BIP-4 Error Interrupt is enabled,
then the XRT72L56 Framer IC will generate an inter-
rupt, anytime the Receive E3 Framer block has de-
tected an error in the BIP-4 Nibble, within an incom-
ing E3 frame.
NOTE: This interrupt is only active if the XRT72L56 Framer
IC has been configured to process the BIP-4 nibble within
each incoming and outbound E3 frame.
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