XRT72L56 Datasheet, PDF (217/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
FIGURE 70. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND TXNEG
ARE CONFIGURED TO BE UPDATED ON THE RISING EDGE OF TXLINECLK
t32
TxLineClk
t30
t33
TxPOS
TxNEG
FIGURE 71. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND TXNEG
ARE CONFIGURED TO BE UPDATED ON THE FALLING EDGE OF TXLINECLK
t32
TxLineClk
t31
t33
TxPOS
TxNEG
4.2.6 Transmit Section Interrupt Processing
The Transmit Section of the XRT72L56 can generate
an interrupt to the Microcontroller/Microprocessor for
the following two reasons.
• Completion of Transmission of FEAC Message
• Completion of Transmission of LAPD Message
4.2.6.1 Enabling Transmit Section Interrupts
As mentioned in Section 1.6, the Interrupt Structure,
within the XRT72L56 contains two hierarchical levels:
• Block Level
• Source Level
The Block Level
The Enable State of the Block Level for the Transmit
Section Interrupts dictates whether or not interrupts
(if enabled at the source level), are actually enabled.
The user can enable or disable these Transmit Sec-
tion interrupts, at the Block Level by writing the appro-
priate data into Bit 1 (Tx DS3/E3 Interrupt Enable)
within the Block Interrupt Enable register (Address =
0x04), as illustrated below.
198