XRT72L56 Datasheet, PDF (259/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04)
BIT 7
RxDS3/E3
Interrupt
Enable
R/W
X
BIT 6
RO
0
BIT 5
RO
0
BIT 4
Not Used
RO
0
BIT 3
RO
0
BIT 2
RO
0
BIT 1
TxDS3/E3
Interrupt
Enable
R/W
0
BIT 0
One Second
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables the Receive Sec-
tion (at the Block Level) for interrupt generation. Con-
versely, setting this bit-field to “0” disables the Re-
ceive Section for interrupt generation.
4.3.6.2 Enabling/Disabling and Servicing
Receive Section Interrupts
As mentioned earlier, the Receive Section of the
XRT72L56 Framer IC contains numerous interrupts.
The Enabling/Disabling and Servicing of each of
these interrupts is described below.
4.3.6.2.1 The Change of State on Receive LOS
Interrupt
If the Change of State on Receive LOS (Loss of Sig-
nal) Interrupt is enabled, then the XRT72L56 Framer
IC will generate an interrupt in response to either of
the following conditions.
1. When the XRT72L56 Framer IC declares an LOS
(Loss of Signal) condition, and
2. When the XRT72L56 Framer IC clears the LOS
(Loss of Signal) condition.
Conditions causing the XRT72L56 Framer IC to
declare an LOS condition
• If the XRT7300 LIU IC declares an LOS condition,
and drives the RLOS input pin (of the XRT72L56
Framer IC) "High".
• If the XRT72L56 Framer IC detects a 180 consecu-
tive “0’s”, via the RxPOS and RxNEG input pins.
Conditions causing the XRT72L56 Framer IC to
clear the LOS condition.
• When the XRT7300 LIU IC ceases declaring an
LOS condition and drives the RLOS input pin (of
the XRT72L56 Framer IC) "Low".
• When the XRT72L56 Framer IC detects at least 60
marks (via the RxPOS and RxNEG input pins) out
of 180 bit-periods.
Enabling and Disabling the Change of State on
Receive LOS Interrupt:
The user can enable or disable the Change of State
on Receive LOS Interrupt, by writing the appropriate
value into Bit 6 (LOS Interrupt Enable) within the
RxDS3 Interrupt Enable Register, as illustrated below.
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)
BIT 7
CP Bit Error
Interrupt
Enable
R/W
0
BIT 6
LOS
Interrupt
Enable
R/W
0
BIT 5
AIS
Interrupt
Enable
R/W
0
BIT 4
Idle Interrupt
Enable
R/W
0
BIT 3
FERF
Interrupt
Enable
R/W
0
BIT 2
AIC
Interrupt
Enable
R/W
0
BIT 1
OOF
Interrupt
Enable
R/W
0
BIT 0
P-Bit Error
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Servicing the Change of State on Receive LOS In-
terrupt
Whenever the XRT72L56 Framer IC detects this in-
terrupt, it will do all of the following.
• It will assert the Interrupt Request output pin (INT)
by driving this pin "Low".
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