XRT72L56 Datasheet, PDF (79/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
For subsequent write operations, within this burst I/O
access, the µC/µP simply repeats steps B.1 through
B.3, as illustrated in Figure 32.
FIGURE 32. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING SUBSEQUENT WRITE OPERATIONS
WITHIN THE BURST I/O CYCLE
ALE_AS
A(11:0)
Address of "Initial" Target Register (Offset = 0x00)
CS
D(7:0)
Data Written at Offset = 0x01
Data Written at Offset = 0x02
RD_DS
WR_R/W
RDY_DTCK
2.3.2.2.1.2.3 Terminating the Burst I/O Access
Burst Access Operation will be terminated upon the
rising edge of the ALE_AS input signal. At this point
the Framer will cease to internally increment the
latched address value. Further, the µC/µP is now free
to execute either a Programmed I/O access or to start
another Burst Access Operation with the XRT72L56
DS3/E3 Framer.
2.3.2.2.2 Burst I/O Access in the Motorola
Mode
If the XRT72L56 DS3/E3 Framer is interfaced to a
Motorola-type µC/µP (e.g., the MC680x0 family, etc.),
then it should be configured to operate in the Motoro-
la mode (by tying the MOTO pin to VCC). Motorola-
type Read and Write Burst I/O Access operations are
described below.
2.3.2.2.2.1 The Motorola-Mode Read Burst I/O
Access Operation
Whenever a Motorola-type µC/µP wishes to read the
contents of numerous registers or buffer locations
over a contiguous range of addresses, then it should
do the following.
a. Perform the initial Read operation of the burst
access.
b. Perform the remaining read operations in the
burst access.
c. Terminate the burst access operation.
Each of these operations, within the Burst Access are
discussed below.
2.3.2.2.2.1.1 The Initial Read Operation
The initial read operation of a Motorola-type read
burst access is accomplished by executing a Pro-
grammed I/O Read cycle, as summarized below.
A.0 Execute a Single Ordinary (Programmed I/
O) Read Cycle, as described in steps A.1
through A.8 below.
A.1 Assert the ALE_AS (AS*) input pin by toggling
it "Low". This step enables the Address Bus
input drivers (within the XRT72L56 DS3/E3
Framer) within the Framer Microprocessor
Interface Block.
A.2 Place the address of the initial target register or
buffer location (within the Framer), on the
Address Bus input pins, A[11:0].
A.3 At the same time, the Address-Decoding cir-
cuitry (within the user's system) should assert
the CS (Chip Select) input pins of the Framer
by toggling it "Low". This action enables further
communication between the µC/µP and the
Framer Microprocessor Interface block.
A.4 After allowing the data on the Address Bus pins
to settle (by waiting the appropriate Address
Setup time), the µC/µP should toggle the
ALE_AS input pin "High". This step causes the
Framer device to latch the contents of the
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