XRT72L56 Datasheet, PDF (268/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17)
BIT 7
RO
0
BIT 6
Not Used
RO
0
BIT 5
RO
0
BIT 4
FEAC Valid
RO
0
BIT 3
RxFEAC
Remove
Interrupt
Enable
R/W
0
BIT 2
RxFEAC
Remove
Interrupt
Status
RUR
0
BIT 1
RxFEAC
Valid
Interrupt
Enable
R/W
X
BIT 0
RxFEAC
Valid
Interrupt
Status
RUR
0
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Servicing the Receive FEAC Message - Validation
Interrupt.
Whenever the XRT72L56 Framer IC generates this
interrupt, it will do the following.
• It will assert the Interrupt Request output pin (INT)
by driving it "Low".
• It will set Bit 0 (RxFEAC Valid Interrupt Status),
within the RxDS3 FEAC Interrupt Enable/Status
Register to “1”, as indicated below.
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17)
BIT 7
RO
0
BIT 6
Not Used
RO
0
BIT 5
RO
0
BIT 4
FEAC Valid
RO
0
BIT 3
RxFEAC
Remove
Interrupt
Enable
R/W
0
BIT 2
RxFEAC
Remove
Interrupt
Status
RUR
0
BIT 1
RxFEAC
Valid
Interrupt
Enable
R/W
1
BIT 0
RxFEAC
Valid
Interrupt
Status
RUR
1
• It will write the contents of this validated FEAC
Message into the Rx DS3 FEAC Register, as indi-
cated below.
RXDS3 FEAC REGISTER (ADDRESS = 0X16)
BIT 7
Not Used
RO
0
BIT 6
RO
0
BIT 5
RO
0
BIT 4
BIT 3
RxFEAC[5:0]
RO
R/O
0
0
BIT 2
R/O
0
BIT 1
R/O
0
BIT 0
Not Used
R/O
0
Whenever the Terminal Equipment encounters the
Receive FEAC Message - Validation Interrupt, then it
should do the following.
• It should read the contents of the High RxDS3
FEAC Register, and respond accordingly.
4.3.6.2.10 The Receive FEAC Message -
Removal Interrupt
if the Receive FEAC Message - Removal Interrupt is
enabled, then the XRT72L56 Framer IC will generate
an interrupt any time the High Receive FEAC Proces-
sor removes a new FEAC (Far-End Alarm & Control)
Message.
In particular, the Receive FEAC Processor will re-
move a FEAC Message, it has received a different
FEAC Message (from the most recently validated
message) in 3 of the last 10 FEAC Message recep-
tions.
Enabling/Disabling the Receive FEAC Message -
Removal Interrupt
The user can enable or disable the Receive FEAC
Message - Removal Interrupt, by writing the appropri-
ate data into Bit 1 (RxFEAC Remove Interrupt En-
able) within the RxDS3 FEAC Interrupt Enable/Status
Register, as indicated below.
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