XRT72L56 Datasheet, PDF (93/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
Setting this bit-field to “1” enables the PRBS Receiver
within the channel. Setting this bit-field to “0” disables
the PRBS Receiver.
Bit 2 - Tx PRBS Enable
This Read/Write bit-field permits the user to enable
the PRBS Generator within the channel.
Setting this bit-field to “1” enables the PRBS Genera-
tor within the channel. Setting this bit-field to “0” dis-
ables the PRBS Generator.
Receive DS3 Framer Configuration Registers
2.4.2.8 Receive DS3 Configuration & Status
Register
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
RxAIS
RxLOS
RxIdle
RxOOF
Reserved
Framing On
Parity
RO
RO
RO
RO
RO
R/W
0
0
0
0
0
0
BIT 1
FSync
Algo
R/W
0
BIT 0
MSync
Algo
R/W
0
Bit 7 - RxAIS (Receive AIS Pattern) Indicator
This Read-Only bit-field indicates whether or not the
Receive Section of the channel, within the XRT72L56
is currently receiving an AIS pattern or not.
The channel will set this bit-field to "0" if it is not cur-
rently detecting an AIS pattern in the incoming data
stream. Conversely, the channel will set this bit-field
to "1" if it is currently receiving an AIS pattern in the
incoming data stream.
NOTE: For a more detailed discussion on the AIS pattern
for DS3 applications, please see Section 3.3.2.5.2
Bit 6 - RxLOS (Receive LOS Condition) Indicator
This Read-Only bit-field indicates whether or not the
Receive Section of the channel (within the Framer de-
vice) is currently declaring an LOS (Loss of Signal)
condition of the incoming DS3 or E3 data stream.
If this bit-field is set to "0", then the Receive Section
(of the channel) is currently not declaring an LOS
condition.
If this bit-field is set to "1", then the Receive Section
(of the channel) is currently declaring an LOS condi-
tion.
NOTE: For more information on the LOS Declaration crite-
ria, for DS3 and E3 applications, please see Section
3.3.2.5.2.
Bit 5 - RxIdle (Receive Idle Pattern) Indicator
This Read-Only bit-field indicates whether or not the
Receive Section of the channel (within the Framer de-
vice) is currently detecting the Idle-pattern in the in-
coming DS3 data stream.
If this bit-field is set to "0" then the Receive Section
(of the channel) is currently not detecting the Idle-pat-
tern in the incoming DS3 data stream.
If this bit-field is set to "1" then the Receive Section
(of the channel) is currently detecting the Idle pattern
in the incoming DS3 data stream.
NOTES:
1. This bit-field is only relevant for DS3 applications.
2. For more information on the Idle Pattern, please
see Section 3.3.2.5.3
Bit 4 - RxOOF (Receive Out-of-Frame) Indicator
This Read-Only bit-field indicates whether or not the
Receive Section of the channel (within the Framer de-
vice) is currently declaring an OOF (Out of Frame)
condition.
If this bit-field is set to "0", then the Receive Section
(of the channel) is currently not declaring the OOF
condition.
If this bit-field is set to "1", then the Receive Section
(of the chip) is currently declaring the OOF condition.
NOTE: For more information on the OOF Declaration crite-
ria, for DS3 applications, please see Section 3.3.2.2.
Bit 3 - Reserved.
Bit 2 - Framing On Parity ON/OFF Select
This Read/Write bit field allows the user to require
that the Receive DS3/E3 Framer block (within the
channel) include Parity (P-bit) verification as a condi-
tion for declaring itself In-Frame, during Frame Acqui-
sition. This requirement will be imposed in addition to
those criteria selected via Bits 0 and 1 of this register.
This feature also imposes an additional Frame Main-
tenance requirement on the Receive DS3/E3 Framer
block, in addition to the requirements specified in the
user's selection of Bits 0 and 1 of this register. In par-
ticular, if this additional requirement is implemented,
the Receive DS3/E3 Framer block will perform a
frame search if it detects P-bit errors in at least 2 out
of 5 DS3 Frames. Writing a "1" to this bit-field impos-
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