XRT72L56 Datasheet, PDF (144/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
PMON CP-BIT ERROR COUNT REGISTER - LSB (ADDRESS = 0X59)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
CP-Bit Error Count - Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
BIT 1
RUR
0
BIT 0
RUR
0
This Reset-upon-Read register, along with the PMON
CP-Bit Error Count Register - MSB (Address = 0x58)
contains a 16-bit representation of the number of CP-
bit Errors that have been detected by the Receive
DS3/E3 Framer block (within the channel), since the
last read of these registers. This register contains the
LSB (or Lower-Byte) value of this 16 bit expression.
NOTE: This register is only active if the Channel has been
configured to operate in the DS3, C-bit Parity Framing for-
mat.
2.4.8.11 PMON Holding Register
PMON HOLDING REGISTER (ADDRESS = 0X6C)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
PMON Holding Value
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
Each of the “above-defined” PMON registers are 16
bit Reset-upon-Read registers. However, the bi-drec-
tional data bus (of the Framer IC) is only 8-bits wide.
As a consequence, whenever the Microprocessor in-
tends to read a PMON register, there are two things
to bear in mind.
1. This Microprocessor is going to require two read
accesses in order read out the full 16-bit expres-
sion of these PMON registers.
2. The entire 16-bit expression (of a given PMON
register) is going to be reset to 0x0000, immedi-
ately after the Microprocessor has completed its
first read access to the PMON register.
Hence, the contents of the other byte (of the partially
read PMON register) will reside within the PMON
Holding register.
2.4.8.12 One-Second Error Status Register
ONE-SECOND ERROR STATUS REGISTER (ADDRESS = 0X6D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Errored
Second
Severely
Errored
Second
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
Bit 1 - Errored Second
This bit field indicates whether or not an error has oc-
curred within the last One-Second accumulation in-
terval. This bit-field will be set to “1” if at least one er-
ror has occurred during the last One-Second accu-
mulation interval. Conversely, this bit-field will be set
to "0" if no errors has occurred during the last one-
second accumulation interval.
Bit 0 - Severely Errored Second
This bit-field indicates whether or not the error rate in
the last one-second interval was greater than 1 in
1000. A "0" indicates that the error rate did not ex-
ceed 1 in 1000 in the last One-Second interval.
2.4.8.13 One-Second Line Code Violation Accu-
mulator Register - MSB
125