XRT72L56 Datasheet, PDF (92/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
2.4.2.7 Test Register
TEST REGISTER (ADDRESS = 0X0C)
BIT 7
TxOH
Source
Select
BIT 6
Rx
Payload
Clock
Enable
BIT 5
Tx
Payload
Clock
Enable
R/W
R/W
R/W
0
0
0
BIT 4
Rx
PRBS
Lock
RO
0
BIT 3
Rx
PRBS
Enable
R/W
0
BIT 2
Tx
PRBS
Enable
R/W
0
áç
PRELIMINARY
BIT 1
BIT 0
Reserved
RO
RUR
0
0
Bit 7 - TxOH Source Select
This Read/Write bit-field permits the user to configure
the Transmit Section of the channel to accept over-
head bits/bytes via the TxSer[n]or TxNib[3:0][n] input
pins.
Setting this bit-field to “1” configures the Transmit
Section of the channel to accept overhead bits/bytes
via either the TxSer[n] or TxNib[3:0][n]input pins.
Setting this bit-field to “0” configures the Transmit
Section of the channel to either internally generate or
accept the overhead bits/bytes via the TxOH[n] input
pin.
Bit 6 - Rx Payload Clock Enable
This Read/Writebit-field permits the user to configure
the Receive Payload Data Output Interface block to
output the receive data in a gapped-clockmanner. If
the user chooses this option, then the Receive Pay-
load Data Output Interface will only generate a clock
edge (via the RxClk[n] output pin) whenever a pay-
load bit is being output via the RxSer[n] output pin.
The Receive Payload Data Output Interface will not
generate a clock edge (via the RxClk[n] output pin)
whenever an overhead bit is being output via the Rx-
Ser[n]output pin.
If the user does not select this option then the Re-
ceive Payload Data Output Interface block will gener-
ate a clock edge for all bits (payload and overhead);
as they are output via the RxSer[n] output pin. How-
ever, the Receive Payload Data Output Interface will
also pulse the RxOHInd[n] output pin “High” each
time an overhead bit is being output via the RxSer[n]
output pin.
Setting this bit-field to “1” enables this feature. Set-
ting this bit-field to “0” disables this feature.
Bit 5 - Tx Payload Clock Enable
This Read/Write bit-field permits the user to configure
the TxOHInd[n] output pin to function as either of the
following roles.
1. The Transmit Overhead Data Output Indicator
2. The Transmit Payload Data Clock Output signal.
If the TxOHInd[n] output pin is configured to function
as the Transmit Overhead Data Output signal, then
this output pin will pulse “High” one bit-period prior to
the instant that the Transmit Section of the channel
(within the XRT72L56 device) is processing an over-
head bit.
If the TxOHInd[n] output pin is configured to function
as the Transmit Payload Data Clock output signal,
then the Transmit Payload Data Output interface
block will generate a clock edge via the TxOHInd[n]
output pin. The Local Terminal equipment is expect-
ed to output outbound payload data to the Transmit
Payload Data Input Interface block (via the TxSer[n]
input pin) upon the falling edge of this clock signal.
NOTE: In this mode, the TxOHInd_n output pin will not gen-
erate a clock edge, whenever the Transmit Section of the
XRT72L56 device is about to process an overhead bit.
Setting this bit-field to “0” configures the TxOHInd[n]
output pin to function as the Transmit Overhead Data
Output signal. Setting this bit-field to “1” configures
the TxOHInd[n] output pin to function as the Transmit
Payload Data Clock output signal.
Bit 4 - Rx PRBS Lock
This Read-Only bit-field indicates whether or not the
PRBS Receiver has acquired PRBS Lock (or Pattern
Sync) with the data generated by the PRBS Genera-
tor.
If this bit-field is set to “1”, then the PRBS Receiver
has acquired PRBS lock with the data generated by
the PRBS Generator. If this bit-field is set to “0”, then
the PRBS Receiver has NOT acquired PRBS Lock
with the data generated by the PRBS Generator.
NOTE: This bit-field is only valid if both the RxPRBS Enable
and Tx PRBS Enable bit-fields are both set to “1”.
Bit 3 - Rx PRBS Enable
This Read/Write bit-field permits the user to enable
the PRBS Receiver within the channel.
73