XRT72L56 Datasheet, PDF (359/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RxDS3/E3
Interrupt
Enable
Not Used
R/W
RO
RO
RO
RO
X
0
0
0
0
BIT 2
RO
0
BIT 1
TxDS3/E3
Interrupt
Enable
R/W
0
BIT 0
One-Second
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables the Receive Sec-
tion at the Block Level) for interrupt generation. Con-
versely, setting this bit-field to “0” disables the Re-
ceive Section for interrupt generation.
5.3.6.2 Enabling/Disabling and Servicing Inter-
rupts
As mentioned previously, the Receive Section of the
XRT72L56 Framer IC contains numerous interrupts.
The Enabling/Disabling and Servicing of each of
these interrupts is described below.
5.3.6.2.1 The Change in Receive LOS Condi-
tion Interrupt
If the Change in Receive LOS Condition Interrupt is
enabled, then the XRT72L56 Framer IC will generate
an interrupt in response to either of the following con-
ditions.
1. When the XRT72L56 Framer IC declares an LOS
(Loss of Signal) Condition, and
2. When the XRT72L56 Framer IC clears the LOS
condition.
Conditions causing the XRT72L56 Framer IC to
declare an LOS Condition.
• If the XRT7300 LIU IC declares an LOS condition,
and drives the RLOS input pin (of the XRT72L56
Framer IC) “High”.
• If the XRT72L56 Framer IC detects 32 consecutive
“0”, via the RxPOS and RxNEG input pins.
Conditions causing the XRT72L56 Framer IC to
clear the LOS Condition.
• If the XRT7300 LIU IC clears the LOS condition and
drives the RLOS input pin (of the XRT72L56
Framer IC) “Low”.
• If the XRT72L56 Framer IC detects a string of 32
consecutive bits (via the RxPOS and RxNEG input
pins) that does NOT contain a string of 4 consecu-
tive “0’s”.
Enabling and Disabling the Change in Receive
LOS Condition Interrupt
The user can enable or disable the Change in Re-
ceive LOS Condition Interrupt, by writing the appro-
priate value into Bit 1 (LOS Interrupt Enable), within
the RxE3 Interrupt Enable Register - 1, as indicated
below.
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
COFA
Interrupt
Enable
OOF
Interrupt
Enable
LOF
Interrupt
Enable
LOS
Interrupt
Enable
AIS
Interrupt
Enable
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
X
0
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Servicing the Change in Receive LOS Condition
Interrupt
Whenever the XRT72L56 Framer IC detects this in-
terrupt, it will do all of the following.
• It will assert the Interrupt Request output pin (INT),
by driving it “Low”.
• It will set Bit 1 (LOS Interrupt Status), within the Rx
E3 Interrupt Status Register - 1 to “1”, as indicated
below.
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