XRT72L56 Datasheet, PDF (142/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
áç
PRELIMINARY
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - MSB (ADDRESS = 0X52)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Framing Bit/Byte Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
BIT 0
RUR
0
This Reset-upon-Read register, along with the PMON
Framing Bit/Byte Error Count Register - LSB (Ad-
dress = 0x53) contains a 16-bit representation of the
number of Framing Bit or Byte Errors that have been
detected by the Receive DS3/E3 Framer block, since
the last read of these registers. This register contains
the MSB (or Upper-Byte) value of this 16 bit expres-
sion.
2.4.8.4 PMON Framing Bit/Byte Error Count
Register - LSB
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - LSB (ADDRESS = 0X53)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Framing Bit/Byte Error Count - Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
BIT 0
RUR
0
This Reset-upon-Read register, along with the PMON
Framing Bit/Byte Error Count Register - MSB (Ad-
dress = 0x52) contains a 16-bit representation of the
number of Framing Bit or Byte Errors that have been
detected by the Receive DS3/E3 Framer block, since
the last read of these registers. This register contains
the LSB (or Lower-Byte) value of this 16 bit expres-
sion.
2.4.8.5 PMON Parity Error Count Register -
MSB
PMON PARITY ERROR COUNT REGISTER - MSB (ADDRESS = 0X54)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Parity Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
BIT 1
RUR
0
BIT 0
RUR
0
This Reset-upon-Read register, along with the PMON
Parity Error Count Register - LSB (Address = 0x55)
contains a 16-bit representation of the number of P-
bit Errors (for DS3 applications), BIP-4 Errors (for E3/
ITU-T G.751 applications) or BIP-8 Errors (for E3/
ITU-T G.832 applications) that have been detected by
the Receive DS3/E3 Framer block, since the last read
of these registers. This register contains the MSB (or
Upper-Byte) value of this 16 bit expression.
2.4.8.6 PMON Parity Error Count Register -
LSB
PMON PARITY ERROR COUNT REGISTER - LSB (ADDRESS = 0X55)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Parity Error Count - Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
123