XRT72L56 Datasheet, PDF (464/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
FIGURE 212. ILLUSTRATION OF THE SIGNALS THAT ARE OUTPUT VIA THE RECEIVE OVERHEAD DATA OUTPUT INTER-
FACE BLOCK (FOR METHOD 2).
Terminal Equipment Signals
RxOutClk
Rx_E3_Clock_In
E3_Data_In[3:0]
Rx_Start_of_Frame
Rx_E3_OH_Ind
Overhead Nibble [0]
Overhead Nibble [1]
XRT72L5x Receive Payload Data I/F Signals
RxOutClk
RxClk
RxNib[3:0]
RxFrame
Overhead Nibble [0]
Overhead Nibble [1]
RxOH_Ind
E3 Frame Number N
Note: RxFrame pulses high to denote
E3 Frame Boundary.
E3 Frame Number N + 1
Recommended Sampling Edge of Terminal
Equipment
6.3.6 Receive Section Interrupt Processing
The Receive Section of the XRT72L56 can generate
an interrupt to the MIcrocontroller/Microprocessor for
the following reasons.
• Change in Receive LOS Condition
• Change in Receive OOF Condition
• Change in Receive LOF Condition
• Change in Receive AIS Condition
• Change in Receive FERF Condition
• Change of Framing Alignment
• Change in Receive Trail Trace Buffer Message
• Detection of FEBE (Far-End Block Error) Event
• Detection of BIP-8 Error
• Detection of Framing Byte Error
• Detection of Payload Type Mismatch
• Reception of a new LAPD Message
6.3.6.1 Enabling Receive Section Interrupts
As mentioned in Section 1.6, the Interrupt Structure
within the XRT72L56 contains two hierarchical levels.
• Block Level
• Source Level
The Block Level
The Enable state of the Block level for the Receive
Section Interrupts dictates whether or not interrupts
(if enabled at the source level), are actually enabled.
The user can enable or disable these Receive Sec-
tion interrupts, at the Block Level by writing the appro-
priate data into Bit 7 (Rx DS3/E3 Interrupt Enable)
within the Block Interrupt Enable register (Address =
0x04), as illustrated below.
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