XRT72L56 Datasheet, PDF (4/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
áç
PRELIMINARY
TABLE 4: PIN DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS WHILE THE MICROPROCESSOR IN-
TERFACE IS OPERATING IN THE MOTOROLA MODE ..................................................................................... 50
2.3 INTERFACING THE XRT72L56 DS3/E3 FRAMER TO THE LOCAL µC/µP VIA THE MICROPROCESSOR INTERFACE BLOCK
50
2.3.1 Interfacing the XRT72L56 DS3/E3 Framer to the Microprocessor over an 8 bit wide bi-directional Data Bus
50
2.3.2 Data Access Modes ................................................................................................................................ 51
Figure 25. Behavior of Microprocessor Interface signals during an Intel-type Programmed I/O Read Oper-
ation ....................................................................................................................................................... 52
Figure 26. Behavior of the Microprocessor Interface Signals, during an Intel-type Programmed I/O Write
Operation ............................................................................................................................................... 53
Figure 27. Illustration of the Behavior of Microprocessor Interface signals, during a Motorola-type Pro-
grammed I/O Read Operation ............................................................................................................... 54
Figure 28. Illustration of the Behavior of the Microprocessor Interface signal, during a Motorola-type Pro-
grammed I/O Write Operation ............................................................................................................... 55
Figure 29. Behavior of the Microprocessor Interface Signals, during the Initial Read Operation of a Burst
Cycle (Intel Type Processor) ................................................................................................................. 56
Figure 30. Behavior of the Microprocessor Interface Signals, during subsequent Read Operations within
the Burst I/O Cycle ................................................................................................................................ 57
Figure 31. Behavior of the Microprocessor Interface signals, during the Initial Write Operation of a Burst
Cycle (Intel-type Processor) .................................................................................................................. 59
Figure 32. Behavior of the Microprocessor Interface Signals, during subsequent Write Operations within
the Burst I/O Cycle ................................................................................................................................ 60
Figure 33. Behavior of the Microprocessor Interface Signals, during the Initial Read Operation of a Burst
Cycle (Motorola Type Processor) .......................................................................................................... 61
Figure 34. Behavior the Microprocessor Interface Signals, during subsequent Read Operations within the
Burst I/O Cycle (Motorola-type µC/µP) .................................................................................................. 62
Figure 35. Behavior of the Microprocessor Interface signals, during the Initial Write Operation of a Burst
Cycle (Motorola-type Processor) ........................................................................................................... 63
Figure 36. Behavior of the Microprocessor Interface Signals, during subsequent Write Operations with the
Burst I/O Cycle (Motorola-type µC/µP) .................................................................................................. 64
2.4 ON-CHIP REGISTER ORGANIZATION ...................................................................................................................... 64
2.4.1 Framer Register Addressing .................................................................................................................... 64
TABLE 5: REGISTER ADDRESSING OF THE FRAMER PROGRAMMER REGISTERS ......................................... 65
2.4.2 Framer Register Description .................................................................................................................... 68
PART NUMBER REGISTER (ADDRESS = 0X02) .......................................................................................... 71
VERSION NUMBER REGISTER (ADDRESS = 0X03) ..................................................................................... 71
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ........................................................................ 71
BLOCK INTERRUPT STATUS REGISTER (ADDRESS = 0X05) ........................................................................ 72
TEST REGISTER (ADDRESS = 0X0C) ....................................................................................................... 73
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ........................................................... 74
RXDS3 STATUS REGISTER (ADDRESS = 0X11) ........................................................................................ 75
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) ....................................................................... 76
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ....................................................................... 77
RXDS3 SYNC DETECT ENABLE REGISTER (ADDRESS = 0X14) ................................................................ 79
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ............................................... 79
RXDS3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ........................................................................... 80
RXDS3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 81
2.4.3 Receive E3 Framer Configuration Registers (ITU-T G.832) .................................................................... 81
RXE3 CONFIGURATION & STATUS REGISTER 1 (ADDRESS = 0X10) ........................................................... 82
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ........................................................... 83
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) .................................................................... 84
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) .................................................................... 85
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) .................................................................... 85
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) .................................................................... 87
II