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XRT72L56 Datasheet, PDF (269/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17)
BIT 7
RO
0
BIT 6
Not Used
RO
0
BIT 5
RO
0
BIT 4
FEAC Valid
RO
0
BIT 3
RxFEAC
Remove
Interrupt
Enable
R/W
X
BIT 2
RxFEAC
Remove
Interrupt
Status
RUR
0
BIT 1
RxFEAC
Valid
Interrupt
Enable
R/W
X
BIT 0
RxFEAC
Valid
Interrupt
Status
RUR
0
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Servicing the Receive FEAC Message - Validation
Interrupt.
Whenever the XRT72L56 Framer IC generates this
interrupt, it will do the following.
• It will assert the Interrupt Request output pin (INT)
by driving it "Low".
• It will set Bit 2 (RxFEAC Remove Interrupt Status),
within the RxDS3 FEAC Interrupt Enable/Status
Register to “1”, as indicated below.
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17)
BIT 7
RO
0
BIT 6
Not Used
RO
0
BIT 5
RO
0
BIT 4
FEAC Valid
RO
0
BIT 3
RxFEAC
Remove
Interrupt
Enable
R/W
0
BIT 2
RxFEAC
Remove
Interrupt
Status
RUR
0
BIT 1
RxFEAC
Valid
Interrupt
Enable
R/W
1
BIT 0
RxFEAC
Valid
Interrupt
Status
RUR
1
• It will write the delete contents of the most recently
validated FEAC Message from the Rx DS3 FEAC
Register, as indicated below.
RXDS3 FEAC REGISTER (ADDRESS = 0X16)
BIT 7
Not Used
RO
0
BIT 6
RO
X
BIT 5
RO
X
BIT 4
BIT 3
RxFEAC[5:0]
RO
R/O
X
X
BIT 2
R/O
X
BIT 1
R/O
X
BIT 0
Not Used
R/O
0
4.3.6.2.11 The Completion of Reception of a
LAPD Message Interrupt
If the Completion of Reception of a LAPD Message
interrupt is enabled, then the XRT72L56 Framer IC
will generate an interrupt anytime the Receive HDLC
Controller block has received a new LAPD Message
buffer, from the Remote Terminal Equipment, and has
stored the contents of this message in the Receive
LAPD Message Buffer.
Enabling/Disable the Receive LAPD Message In-
terrupt
The user can enable or disable the Receive LAPD
Message Interrupt by writing the appropriate data into
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