XRT72L56 Datasheet, PDF (161/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
Figure 39 presents a simple circuit schematic that de-
picts how the XRT72L56 DS3/E3 Framer IC could be
interfaced to the XRT7300 DS3/E3/STS-1 LIU IC.
FIGURE 39. SCHEMATIC DEPICTING HOW TO INTERFACE THE XRT72L56 DS3/E3 FRAMER IC TO THE XRT73L03
DS3/E3/STS-1 LIU IC (ONE CHANNEL SHOWN)
RxAVDD_0
DVDD_0
RxAIS_Ch_0
RxRED_ALARM_0
Rx_OOF_Ch_0
Rx_LOS_Ch_0
RxFRAME_0
RxSERIAL_CLK_0
RxDATA_IN_0
D[7:0]
A[11:0]
READY_OUT*
ALE
RD*
WR*
XRT72L56_CS*
XRT72L56_INT*
HW_RESET*
TxFRAME_0
44.736MHz
TxDATA_OUT_0
U3
D9
A7
B8
A8
RxAIS_0
RxRED_0
RxOOF_0
RxLOS_0
A9
B9
C9
T25
RxFrame_0
RxClk_0
RxSer_0
MOTO
RxPOS_0 ^H2
RxNEG_0 ^G1
K23
J26
D7
K24
K25
L23
L24
L25
L26
D6
D5
D4
D3
D2
D1
D0
R26
P25
P24
P23
P26
N26
N25
N24
N23
M26
M25
M24
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
J25
R24
U26
R23
T23
J24
Rdy_Dtck
ALE_AS
RD_DS
WR_RW
CS
INT
T24 _RESET
RxLineClk_0 ^J4
RLOL_0
ExtLOS_0
B6
J3
LLOOP_0
REQB_0
TAOS_0
DMO_0
TxLEV_0
C8
B7
C7
D8
D6
RLOOP_0 ^D10
ENCODIS_0 (TxOFF_0) ^C6
TxPOS_0 ^J1
TxNEG_0 ^K4
TxLineClk_0 ^J2
R25 _NIBBLEINTF
B12
H3
C15
TxFrame_0
TxInClk_0
TxSer_0
XRT72L56_Ch_0
C4
0.01uF
C5
0.01uF
R7
4.7k
70 _RxAVDD0
48 _RxDVDD0
67
42
LOSTHR_0
HOST/HW
51 _RPOS0
50 _RNEG0
49 _RCLK0
U2
TxAVDD0 ²⁸
TxAVDD0 ³⁷
RTIP0 ⁷²
RRING0 ⁷¹
C2
0.01uF
C3
0.01uF
TxAVDD_0
6 _T2 1
43
T3001
J1
BNC
1
XRT71D03_CS* (Optional)
57
55
RLOL_0
RLOS_0
61
62
63
64
96
CS
SCLK
SDI
SDO
REG_RESET*
117 _{TxOFF_0}
33 _{TPDATA_0}
32 _{TNDATA_0}
34
47
TCLK_0
EXCLK_0
TTIP0 ²⁹
TRING0 ²⁷
MTIP0 ³⁰
54 _RxDGND0
73 _RxAGND0
MRING0 ³¹
TxAGND0 ³⁹
TxAGND0 ²⁶
XRT73L03IV_Ch_0
R1
R2
37.4
37.4
C1
0.01uF
R3
31.6
R4
R5
31.6
270
R6
270
1 _T1 6
34
T3001
J2
BNC
1
3.1 BIT-FIELDS WITHIN THE LINE INTERFACE DRIVE
REGISTER
As mentioned above, the Line Interface Drive and
Scan section consists of five output pins and three in-
put pins. The logic state of the output pins are con-
trolled by the contents within the Line Interface Drive
register, as depicted below.
LINE INTERFACE DRIVE REGISTER (ADDRESS = 0X80)
BIT 7
ILOOP
BIT 6
BIT 5
REQB
BIT 4
TAOS
BIT 3
ENCODIS
BIT 2
TXLEV
BIT 1
RLOOP
BIT 0
LLOOP
R/O
R/O
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
1
0
0
0
The role of each of these bit-fields are their corre-
sponding output pins are depicted below.
Bit 7 - ILOOP (Internal Remote Loop-back)
This “Read/Write” bit-field permits the user to config-
ure the corresponding channel (within the XRT72L56
device) to operate in the “Internal Remote Loop-back”
Mode. Once the user configures the channel to oper-
ate in this remote loop-back mode, then the “Rx-
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