XRT72L56 Datasheet, PDF (90/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
Setting this bit-field to "1" configures the XRT72L56 to
output data, via the TxPOS and TxNEG output pins,
on the falling edge of TxLineClk.
Bit 1 - RxLineClk Invert
This Read/Write bit-field permits the user to configure
the XRT72L56 to latch data on the RxPOS and Rx-
NEG input pins, into the XRT72L56, on the rising or
falling edge of RxLineClk.
Setting this bit-field to "0" configures the XRT72L56 to
latch the data on the RxPOS and RxNEG input pins,
into the device, on the rising edge of RxLineClk.
Setting this bit-field to "1" configures the XRT72L56 to
latch the data on the RxPOS and RxNEG input pins,
into the device, data, on the falling edge of RxLineClk.
Bit 0 - Reframe
This Read/Write bit-field permits the user to configure
the Receive Section of the XRT72L56 to start a new
frame search. A "0" to "1" transition, in this bit-field
will force the chip to start a new frame search.
2.4.2.3 Part Number Register
PART NUMBER REGISTER (ADDRESS = 0X02)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Part Number Value
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
1
0
0
1
The “Part Number” register can be used by System-
level software to identify this particular device as the
XRT72L56 3-Channel DS3/E3 Framer IC. The value
of the “Part Number” register, within this device is
“0x09”.
2.4.2.4 Version Number Register
The “Version Number” register permits the user’s
software to identify the revision number of the part.
The very first revision of the part will contain the value
“0x01”.
VERSION NUMBER REGISTER (ADDRESS = 0X03)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Version Number Value
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
1
2.4.2.5 Block Interrupt Enable Register
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RxDS3/E3
Interrupt
Enable
Not Used
R/W
RO
RO
RO
RO
0
0
0
0
0
BIT 2
RO
0
BIT 1
TxDS3/E3
Interrupt
Enable
R/W
0
BIT 0
One-Second
Interrupt
Enable
R/W
0
Bit 7 - RxDS3/E3 Interrupt Enable
This Read/Write bit-field permits the user to enable or
disable all Receive Section related interrupts (within
the XRT72L56), at the Block Level.
Setting this bit-field to "0" disables all Receive Section
related Interrupts within the XRT72L56.
Setting this bit-field to "1" enables the Receive Sec-
tion related Interrupts (within the XRT72L56) at the
block level.
NOTE: Setting this bit-field to "1" does not enable all
Receive Section related Interrupts. Each of these interrupts
can still be disabled at the Source Level. However, setting
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