XRT72L56 Datasheet, PDF (51/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
AC ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: TA = 25(C, VCC = 3.3V + 5% unless otherwise specified
SYMBOL
PARAMETER
MIN. TYP.
t₂₇ TxInClk clock (falling) edge to “TxOHIns” hold-time 100
50
MAX.
UNITS
CONDITIONS
ns DS3 Applications
ns E3, ITU-T G.832
Applications
12
t₂₈ “TXOHIns” to “TxInClk” (falling edge) set-up Time
920
140
ns E3, ITU-T G.751
Applications
ns DS3 Applications
ns E3, ITU-T G.832
Applications
20
t₂₉ TxInClk clock (falling) edge to “TxOHIns” hold-time 100
50
ns E3, ITU-T G.751
Applications
ns DS3 Applications
ns E3, ITU-T G.832
Applications
12
t_29A “TxOHEnable” to “TxOHIns/TxOH” Delay
1
Transmit LIU Interface Timing (see Figure 9 and Figure 10)
t₃₀ Rising edge of "TxLineClk" to rising edge of
1
2.0
"TxPOS" or "TxNEG" output signal.
(Framer is configured to output data on "TxPOS"
and "TxNEG" on rising edge of "TxLineClk"
t₃₁ Falling edge of "TxLineClk" to rising edge of
1
4
"TxPOS" or "TxNEG"
(Framer is configured to output data via "TxPOS"
and "TxNEG" on falling edge of "TxLineClk")
f_TxLineClk Period of TxLineClk clock signal
44.736
f_TxLineClk Period of TxLineClk clock signal
34.368
t₃₂ Period of TxLineClk
22.36
t32 Period of TxLineClk
Receive LIU Interface Timing (see Figure 11 and Figure 12)
t₃₈ "RxPOS" or "RxNEG" set-up time to rising edge of
3
"RxLineClk".
(Framer is configured to sample data on "RxPOS"
and "RxNEG" input pins, on the rising edge of "RxLi-
neClk")
29.10
ns E3, ITU-T G.751
Applications
ns
ns
ns
MHz DS3 Applications
Mhz E3 Applications
ns DS3 Applications
ns E3 Applications
ns
32