XRT72L56 Datasheet, PDF (436/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
within the Rx E3 Framer Interrupt Status Register -
1.
• Clearing the RxAIS output pin (e.g., toggling it
"Low”).
• Setting the RxAIS bit-field, within the Rx E3 Config-
uration & Status Register to “0”, as depicted below.
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Rx LOF Algo RxLOF
RxOOF
RxLOS
RxAIS
RxPld Unstab
Rx
TMark
RxFERF
R/W
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
6.3.2.6.3 The Far-End-Receive Failure (FERF)
Condition
Declaring the FERF Condition
The Receive E3 Framer block will declare a Far-End
Receive Failure (FERF) condition if it detects a user-
selectable number of consecutive incoming E3
frames, with the FERF bit-field (Bit 7, within the MA
Byte) set to “1”. Recall, the bit-format of the MA byte
is presented below.
THE MAINTENANCE AND ADAPTATION (MA) BYTE FORMAT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FERF
FEBE
Payload Type
Payload Dependent
Timing Marker
This User-selectable number of E3 frames is either 3 into Bit 4 (Rx FERF Algo) within the Rx E3 Configura-
or 5, depending upon the value that has been written tion & Status Register, as depicted below.
RXE3 CONFIGURATION & STATUS REGISTER 1 - (E3, ITU-T G.832) (ADDRESS = 0X10)
BIT 7
BIT 6
RxPLDType[2:0]
BIT 5
BIT 4
RxFERF
Algo
BIT 3
RxTMark
Algo
BIT 2
BIT 1
RxPLDExp[2:0]
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
BIT 0
RO
0
Writing a “0” into this bit-field causes the Receive E3
Framer block to declare a FERF condition, if it detects
3 consecutive incoming E3 frames, that have the
FERF bit (within the MA byte) set to “1”.
Writing a “1” into this bit-field causes the Receive E3
Framer block to declare a FERF condition, if it detects
5 consecutive incoming E3 frames, that have the
FERF bit (within the MA byte) set to “1”.
Whenever the Receive E3 Framer block declares a
FERF condition, then it will do the following.
• Generate a Change in FERF Condition interrupt to
the MIcroprocessor. Hence, the Receive E3
Framer block will assert Bit 3 (FERF Interrupt Sta-
tus) within the Rx E3 Framer Interrupt Status regis-
ter - 2, as depicted below.
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