XRT72L56 Datasheet, PDF (387/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
FIGURE 166. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT72L56 AND THE TERMINAL
EQUIPMENT (E3 MODE 5 OPERATION)
Terminal Equipment Signals
RxOutClk
E3_Nib_Clock_In
E3_Data_Out[3:0]
Tx_Start_of_Frame
E3_Overhead_Ind
Payload Nibble [1059]
Overhead Nibble [0]
XRT72L5x Transmit Payload Data I/F Signals
RxOutClk
TxNibClk
TxNib[3:0]
TxFrameRef
p
Nibble [1059]
Overhead Nibble [0]
TxOH_Ind
Note: Terminal Equipment pulses
“TxFrameRef” in order to denote
the E3 Frame Boundary.
E3 Frame Number N
E3 Frame Number N + 1
TxOH_Ind pulses high for 4 Nibble periods
How to configure the XRT72L56 into Mode 5
1. Set the NibIntf input pin "High".
2. Set the TimRefSel[1:0] bit-fields (within the
Framer Operating Mode Register) to "01" as illus-
trated below.
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
Local Loopback
BIT 6
DS3/E3*
R/W
R/W
0
0
BIT 5
Internal LOS
Enable
R/W
1
BIT 4
RESET
R/W
0
BIT 3
BIT2
Interrupt Enable Frame Format
Reset
R/W
R/W
1
0
BIT 1
BIT 0
TimRefSel[1:0]
R/W
R/W
0
1
3. Interface the XRT72L56, to the Terminal Equip-
ment, as illustrated in Figure 165.
6.2.1.6 Mode 6 - The Nibble-Parallel/Local-
Timed/Frame-Master Interface Mode Behavior of
the XRT72L56
If the XRT72L56 has been configured to operate in
this mode, then the XRT72L56 will function as fol-
lows:
A. Local Timing - Uses the TxInClk signal as the
Timing Reference
In this mode, the Transmit Section of the XRT72L56
will use the TxInClk signal at its timing reference.
Further, the chip will internally divide the TxInClk
clock signal by a factor of 4 and will output this divid-
ed clock signal via the TxNibClk output pin. The
Transmit Terminal Equipment Input Interface block
(within the XRT72L56) will use the rising edge of the
TxNibClk signal, to latch the data, residing on the Tx-
Nib[3:0] into its circuitry.
B. Nibble-Parallel Mode
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