XRT72L56 Datasheet, PDF (271/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
5.0 E3/ITU-T G.751 OPERATION OF THE
XRT72L56
Configuring the XRT72L56 to Operate in the E3,
ITU-T G.751 Mode
The XRT72L56 can be configured to operate in the
E3/ITU-T G.751 Mode by writing a “0” into bit-field 6
and a “0” into bit-field 2, within the Framer Operating
Mode register, as illustrated below.
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Local
Loopback
DS3/E3*
Internal
LOS
Enable
RESET
R/W
R/W
R/W
R/W
x
0
x
0
Prior to describing the functional blocks within the
Transmit and Receive Sections of the XRT72L56, it is
important to describe the E3, ITU-T G.751 framing
format.
5.1 DESCRIPTION OF THE E3, ITU-T G.751 FRAMES
AND ASSOCIATED OVERHEAD BITS
The role of the various overhead bytes are best de-
scribed by discussing the E3, ITU-T G.751 Frame
Format as a whole. The E3, ITU-T G.751 Frame con-
tains 1536 bits, of which 12 bits are overhead and the
remaining 1524 bits are payload bits.
Each E3, ITU-T G.751 Frame consists of the following
12 overhead bits.
Interrupt
Enable
Reset
Frame
Format
TimRefSel[1:0]
R/W
R/W
R/W
R/W
x
0
x
x
• A 10 bit FAS (Framing Alignment Signal) pattern.
This pattern is assigned the constant pattern of
“1111010000”, and is used by the Receive E3
Framer block to acquire and maintain Frame Syn-
chronization with the incoming E3 frames.
• The “A” (or Alarm) Bit.
• The “N” (or National) Bit.
• The BIP-4 Bits (if configured).
The frame repetition rate for this type of E3 frame is
22375 times per second, thereby resulting in the
standard E3 bit rate of 34.368 Mbps. Figure 97 pre-
sents an illustration of the E3, ITU-T G.751 Frame
Format.
FIGURE 97. ILLUSTRATION OF THE E3, ITU-T G.751 FRAMING FORMAT.
1
10 11 12
Frame
Alignment
Signal
AN
384 385
768 769
1152 1153
1532
1536
Data
Data
Data
Data
BIP-4
if Selected
Framing Alignment Signal Pattern = 1111010000
5.1.1 Definition of the Overhead Bits
Each of these Overhead Bits are further defined be-
low.Frame Alignment Signaling (FAS) Pattern Bits
The first 10 bits, within each E3, ITU-T G.751 frame
are known as the FAS (or Framing Alignment Signal-
ing) bits. The Receive E3 Framer block, while trying
to acquire or maintain framing synchronization with its
incoming E3 frames, will attempt to locate the FAS
bits. The FAS pattern is assigned the value
“1111010000”.
5.1.1.1 The “A” (Alarm) Bit
The “A” bit typically functions as a FERF (Far-End
Receive Failure) indicator bit. However, if the user
configures the XRT72L56 Framer IC to transmit and
receive E3 frames which are carrying the BIP-4 value
(located at the end of a given E3 frame), then this bit
will also function as the FEBE indicator bit. A detailed
discussion on the practical use of the “A” is present-
ed in Section 4.2.2. Each of these roles of the “A” bit
are briefly discussed below.
The “A” Bit Functioning as the FERF bit-field
If the Receive E3 Framer block (at a Local Terminal)
is experiencing problems receiving E3 frame data
from a Remote Terminal (e.g., an LOS, OOF or AIS
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