XRT72L56 Datasheet, PDF (474/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
• It should read the contents of the PMON Parity
Error Event Count Registers (located at Addresses
0x54 and 0x55) in order to determine the number of
BIP-8 Errors that have been received by the
XRT72L56 Framer IC.
6.3.6.2.10 The Detection of Framing Byte Error
Interrupt
If the Detection of Framing Byte Error Interrupt is en-
abled, then the XRT72L56 Framer IC will generate an
interrupt, anytime the Receive E3 Framer block has
received an E3 frame with an incorrect Framing Byte
(e.g., FA1 or FA2) value.
Enabling and Disabling the Detection of FEBE
Event Interrupt
The user can enable or disable the Detection of
Framing Byte Error’ interrupt by writing the appropri-
ate value into Bit 1 (Framing Byte Error Interrupt En-
able) within the Rx E3 Interrupt Enable Register - 2,
as indicated below.
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Enable
R/W
0
BIT 5
Not Used
RO
0
BIT 4
FEBE
Interrupt
Enable
R/W
X
BIT 3
FERF
Interrupt
Enable
R/W
X
BIT 2
BIP-8
Error Interrupt
Enable
R/W
0
BIT 1
Framing
Byte Error
Interrupt
Enable
R/W
0
BIT 0
RxPld
Mis
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Servicing the Detection of Framing Byte Error In-
terrupt
Whenever the XRT72L56 Framer IC detects this in-
terrupt, it will do the following.
• It will assert the Interrupt Request output pin (INT),
by driving it “High”.
• It will set the Bit 4 (Framing Byte Error Interrupt Sta-
tus), within the RxE3 Interrupt Status Register - 2
as indicated below.
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Status
RUR
0
BIT 5
Not Used
RO
0
BIT 4
FEBE
Interrupt
Status
RUR
1
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
BIP-8
Error Interrupt
Status
RUR
0
BIT 1
Framing
Byte Error
Interrupt
Status
RUR
0
BIT 0
RxPld
Mis
Interrupt
Status
RUR
0
Whenever the Terminal Equipment encounters the
Detection of Framing Byte Error Interrupt, it should do
the following.
• It should read the contents of the PMON Framing
Bit/Byte Error Count Registers (located at
Addresses 0x52 and 0x53) in order to determine
the number of Framing Byte errors that have been
received by the XRT72L56 Framer IC.
6.3.6.2.11 The Detection of Payload Type Mis-
match Interrupt
If the Detection of Payload Type Mismatch Interrupt is
enabled, then the XRT72L56 Framer IC will generate
an interrupt, anytime the Receive E3 Framer block re-
ceives a MA byte (within an incoming E3 frame) that
contents a Payload Type value that is different from
the expected Payload Type value.
Conditions causing this interrupt to be generated.
During system configuration, the user is expected to
specify the Payload Type value that is expected of the
Receive E3 Framer to receive (within each E3 frame),
by writing this value into the RxPLDExp[2:0] bit-fields
within the Rx E3 Configuration & Status Register - 1,
as indicated below.
As long as the Receive E3 Framer block receives E3
frames that contains this Payload Type value, no in-
terrupt will be generated. However, the instant that it
receives an E3 frame, that contains a different Pay-
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