XRT72L56 Datasheet, PDF (123/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
NOTE: For information on the LAPD Transmitter, please see
Section 3.2.3.2.
2.4.5.5 Transmit DS3 LAPD Status and Inter-
rupt Register (DS3 Applications)
TXDS3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Not Used
TxDL Start TxDL Busy
RO
RO
RO
RO
R/W
RO
0
0
0
0
0
0
BIT 1
TxLAPD
Interrupt
Enable
R/W
0
BIT 0
TxLAPD
Interrupt
Status
RUR
0
Bit 3 - TxDL Start
This Read/Write bit-field allows the user to invoke the
Transmit LAPD Message command. Once the user
invokes this command, the LAPD Transmitter will do
the following:
• Read in the PMDL Message from the Transmit
LAPD Message Buffer.
• Encapsulate the PMDL Message into a complete
LAPD Message frame by including the necessary
header and trailer bytes (e.g., flag sequence bytes,
SAPI, CR, EA values, etc.).
• Compute the frame check sequence word (16 bit
value)
• Insert the Frame Check Sequence value into the 2
octet slot after the payload section of the Message.
• Proceed to transmit the LAPD Message Frame to
the far end terminal via the outgoing DS3 frames.
Writing a "1" to this bit-field start the transmission of
the LAPD Message Frame, via the LAPD Transmitter.
NOTE: For more information on the LAPD Transmitter,
please see Section 3.2.3.2.
Bit 2 - TxDL Busy
This Read-Only bit-field allows the local µP to poll
and determine if the LAPD Transmitter has completed
its transmission of the LAPD Message frame. This
bit-field will contain a "1", if the LAPD Transmitter is
still transmitting the LAPD Message frame to the far-
end terminal. This bit-field will toggle to "0", once the
LAPD Transmitter has completed its transmission of
the LAPD Message frame.
NOTE: For more information on the LAPD Transmitter,
please see Section 3.2.3.2.
Bit 1 - TxLAPD Interrupt Enable
This Read/Write bit-field allows the user to enable or
disable the LAPD Message Frame Transmission
Complete interrupt.
Writing a "0" to this bit-field disables this interrupt.
Writing a "1" to this bit-field enables this interrupt.
Bit 0 - TxLAPD Interrupt Status
This Reset Upon Read bit-field indicates whether or
not the LAPD Message frame Transmission Complete
interrupt has occurred since the last read of this reg-
ister. The purpose of this interrupt is to let the local
µP know that the LAPD Transmitter has completed its
transmission of the LAPD Message frame (containing
the latest PMDL message) and is now ready to trans-
mit another LAPD Message frame.
A "0" in this bit-field indicates that the LAPD Message
frame Transmission Complete interrupt has not oc-
curred since the read of this register. A "1" in this bit-
field indicates that this interrupt has occurred since
the last read of this register.
NOTE: For more information on the TxLAPD Interrupt,
please see Section 3.2.6.
2.4.5.6 Transmit DS3 M-Bit Mask Register
(DS3 Applications)
TXDS3 M-BIT MASK REGISTER (ADDRESS = 0X35)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxFEBEDat[2:0]
FEBE Reg
Enable
Tx Error
P-Bit
MBit Mask[2] MBit Mask[1] MBit Mask[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
104