XRT72L56 Datasheet, PDF (395/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
TABLE 74: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN TXOHCLK, (SINCE
"TXOHFRAME" WAS LAST SAMPLED "HIGH") TO THE E3 OVERHEAD BIT, THAT IS BEING PROCESSED
NUMBER OF RISING CLOCK EDGES IN
TXOHCLK
THE OVERHEAD BIT EXPECTED BY THE CAN THIS OVERHEAD BIT BE ACCEPTED BY
"XRT72L56"
THE XRT72L56?
0 (Clock edge is coincident with TxO-
FA1 Byte - Bit 7
No
HFrame being detected “High”)
1
FA1 Byte - Bit 6
No
2
FA1 Byte - Bit 5
No
3
FA1 Byte - Bit 4
No
4
FA1 Byte - Bit 3
No
5
FA1 Byte - Bit 2
No
6
FA1 Byte - Bit 1
No
7
FA1 Byte - Bit 0
No
8
FA2 Byte - Bit 7
No
9
FA2 Byte - Bit 6
No
10
FA2 Byte - Bit 5
No
11
FA2 Byte - Bit 4
No
12
FA2 Byte - Bit 3
No
13
FA2 Byte - Bit 2
No
14
FA2 Byte - Bit 1
No
15
FA2 Byte - Bit 0
No
16
EM Byte - Bit 7
No
17
EM Byte - Bit 6
No
18
EM Byte - Bit 5
No
19
EM Byte - Bit 4
No
20
EM Byte - Bit 3
No
21
EM Byte - Bit 2
No
22
EM Byte - Bit 1
No
23
EM Byte - Bit 0
No
24
TR Byte - Bit 7
Yes
25
TR Byte - Bit 6
Yes
26
TR Byte - Bit 5
Yes
27
TR Byte - Bit 4
Yes
28
TR Byte - Bit 3
Yes
29
TR Byte - Bit 2
Yes
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