English
Language : 

XRT72L56 Datasheet, PDF (22/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
áç
PRELIMINARY
PIN DESCRIPTION
PIN DESCRIPTION FOR THE XRT72L56
PIN #
PIN NAME
TYPE
DESCRIPTION
A1
REQ[5]
O Receive Equalization Enable/Disable Select output pin - (to be con-
nected to the XRT7300 family DS3/E3 Line Interface Unit ):
Setting this pin high will force the EXAR’s DS3/E3 LIU to bypass the internal
equalizer.
In Host Mode, state of this output pin can be controlled by writing a “0” or “1”
to bit 5 within the Line Interface Drive Register (Address=0x80).
A2
NC
A3
NC
A4
RxRed[5]
O Receiver Red Alarm Indicator - Receive Framer:
The Framer asserts this output pin to denote that one of the following events
has been detected by the Receive Framer:
LOS - Loss of Signal Condition
OOF - Out of Frame Condition
AIS - Alarm Indication Signal Detection
A5
RxAIS[5
O Receive "Alarm Indication Signal" Output pin:
The Framer will assert this pin to indicate that the Alarm Indication Signal
(AIS) has been identified in the Receive DS3 or E3 data stream.
For DS3 Applications:
An "AIS" is detected if the payload consists of the recurring pattern of
1010... and this pattern persists for 63 M-frames. An additional requirement
for AIS indication is that the C-bits are set to 0, and the X-bits are set to 1.
This pin will be negated when a sufficient number of frames, not exhibiting
the "1010..." pattern in the payload has been detected.
For E3 Applications:
The Receive Section will declare an AIS condition, if it detects two consecu-
tive E3 frames, each containing 7 or less "0s".
A7
RxRed[0]
O See Description for Pin A4
A8
RxLOS[0]
O Receive Section - Loss of Signal Output Indicator:
This pin is asserted when the Receive Section encounters a string of 180
consecutive 0's (for DS3 operation) or 32 consecutive 0's (for E3 operation)
via the RxPOS and RxNEG pins.
This pin will be negated once the Receive Section has detected at least 60
pulses within 180 bit-periods (for DS3 operation); or the Receive Section
has detected a string of 32 consecutive bits, that does not contain a string of
4 consecutive "0s" (for E3 operation).
3