XRT72L56 Datasheet, PDF (265/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
Servicing the Change of State on Receive FERF
Interrupt
Whenever the XRT72L56 Framer IC detects this in-
terrupt, it will do all of the following.
• It will assert the Interrupt Request Output pin (INT)
by driving it "High".
• It will set Bit 3 (FERF Interrupt Status), within the
Rx DS3 Interrupt Status Register, to “1”, as indi-
cated below.
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)
BIT 7
CP-Bit Error
Interrupt
Status
RUR
0
BIT 6
LOS
Interrupt
Status
RUR
0
BIT 5
AIS
Interrupt
Status
RUR
0
BIT 4
Idle Interrupt
Status
RUR
0
BIT 3
FERF
Interrupt
Status
RUR
1
BIT 2
AIC
Interrupt
Status
RUR
0
BIT 1
OOF
Interrupt
Status
RUR
0
BIT 0
P-Bit Error
Interrupt
Status
RUR
0
Whenever the Terminal Equipment encounters a
Change in FERF Condition on Receive Interrupt, it
should do the following.
1. It should determine the current state of the FERF
condition. Recall, that this interrupt can gener-
ated, whenever the XRT72L56 Framer declares
RXDS3 STATUS REGISTER (ADDRESS = 0X11)
or clears the FERF condition. Hence, the user
can determine the current state of the FERF con-
dition by reading the state of Bit 5 (RxIdle), within
the RxDS3 Configuration & Status Registers, as
illustrated below
BIT 7
RO
0
BIT 6
Reserved
RO
0
BIT 5
RO
0
BIT 4
RxFERF
RO
0
BIT 3
RxAIC
RO
0
BIT 2
RO
0
BIT 1
RxFEBE[2:0]
RO
0
BIT 0
RO
0
4.3.6.2.6 The Change of State of Receive AIC
Interrupt
If the Change of State of Receive AIC Interrupt is en-
abled, then the XRT72L56 Framer IC will generate an
interrupt, anytime the Receive DS3 Framer block has
detected a change in the value of the AIC bit, within
the incoming DS3 data stream.
Enabling and Disabling the Change of State of
Receive AIC Interrupt:
The user can enable or disable the Change of State
on Receive AIC Interrupt, by writing the appropriate
value into Bit 2 (AIC Interrupt Enable) within the
RxDS3 Interrupt Enable Register, as illustrated below.
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)
BIT 7
CP Bit Error
Interrupt
Enable
R/W
0
BIT 6
LOS
Interrupt
Enable
R/W
0
BIT 5
AIS
Interrupt
Enable
R/W
0
BIT 4
Idle Interrupt
Enable
R/W
0
BIT 3
FERF
Interrupt
Enable
R/W
0
BIT 2
AIC
Interrupt
Enable
R/W
0
BIT 1
OOF
Interrupt
Enable
R/W
0
BIT 0
P-Bit Error
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Servicing the Change of State on Receive AIC In-
terrupt
Whenever the XRT72L56 Framer IC detects this in-
terrupt, it will do all of the following.
• It will assert the Interrupt Request Output pin (INT)
by driving it "High".
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