XRT72L56 Datasheet, PDF (118/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
1. When the Receive DS3/E3 Framer block first
detects the occurrence of an Rx FERF Condition
(e.g., when the FERF bit, within the last 3 or 5
consecutive E3 frames are set to "1").
2. When the Receive DS3/E3 Framer block detects
the end of the Rx FERF Condition (e.g., when the
FERF bit, within the last 3 or 5 consecutive E3
frames are set to "0").
NOTE: For more information on the Rx FERF (Yellow
Alarm) condition, please see Section 4.3.2.9.
Bit 2 - BIP-4 (Detection of BIP-4) Error Interrupt
Status
This Reset-upon-Read bit-field will be set to "1" if the
BIP-4 Error interrupt has occurred since the last read
of this register.
The Receive DS3/E3 Framer block will generate the
BIP-4 Error interrupt if it has concluded that it has re-
ceived an errored E3 frame, from the Remote Termi-
nal.
NOTE: Please see Section 4.3.6.1.7 for a more detailed dis-
cussion of this interrupt.
Bit 1 - Framing Error Interrupt Status
This Reset-upon-Read bit-field will be set to "1" if the
Framing Byte Error interrupt has occurred since the
last read of this register.
The Receive DS3/E3 Framer blockwill generate the
Framing Error interrupt if it has detected an error in
the FAS (or Framing Alignment), in an incoming E3
frame.
NOTE: Please see Section 4.3.6.1.8 for a more detailed dis-
cussion of this interrupt.
2.4.4.7 Receive E3 LAPD Control Register (E3,
ITU-T G.751)
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
RxLAPD
Enable
RxLAPD
Interrupt
Enable
RxLAPD
Interrupt
Enable
RO
RO
RO
RO
RO
R/W
R/W
RUR
0
0
0
0
0
0
0
0
Bit 2 - RxLAPD Enable
This Read/Write bit-field allows the user to enable or
disable the LAPD Receiver, for reception of incoming
LAPD Message frames from the Remote LAPD
Transmitter.
Writing a "1" to this bit-field enables the LAPD Re-
ceiver. Writing a "0" to this bit-field disables the LAPD
Receiver.
Bit 1 - RxLAPD (Received LAPD Message) Inter-
rupt Enable
This Read/Write bit-field allows the user to enable or
disable the Received LAPD Message frame interrupt.
Setting this bit-field to "1" enables this interrupt. Set-
ting this bit-field to "0" disables this interrupt.
NOTE: For more information on this interrupt, please see
Section 4.3.6.1.9.
Bit 0 - RxLAPD (Received LAPD Message) Inter-
rupt Status
This Reset-upon-Read bit-field will be set to "1" if the
Receipt of New LAPD Message frame interrupt has
occurred since the last read of this register.
The Receive DS3/E3 Framer block will generate this
Receipt of New LAPD Message frame interrupt when
the LAPD Receiver has received a complete LAPD
Message frame from the Remote LAPD Transmitter.
NOTE: Please see section 4.3.6.1.9 for a more detailed dis-
cussion of this interrupt.
2.4.4.8 Receive E3 LAPD Status Register (E3,
ITU-T G.751)
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Not Used
RxAbort
RxLAPDType[1:0]
RxCR Type RxFCS Error
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
BIT 1
End of
Message
RO
0
BIT 0
Flag Present
RO
0
99