XRT72L56 Datasheet, PDF (449/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
FIGURE 202. FLOW CHART DEPICTING THE FUNCTIONALITY OF THE LAPD RECEIVER (CONTINUED)
From Figure 184
Generate the “Receive LAPD Message frame” interrupt.
Compute “Frame Check Sequence (FCS)” value of incoming
LAPD Message Frame.
Compare “locally-computed” FCS value with that contained
within the newly received LAPD Message frames.
A
End
Do the
two FCS values
Yes
Match?
No
FCS Error Detected
Assert the “Rx FCS Error” bit-field within the “Rx E3
LAPD Status Register (Address = 0x19).
6.3.4 The Receive Overhead Data Output Inter-
face
Figure 203 presents a simple illustration of the Re-
ceive Overhead Data Output Interface block within
the XRT72L56.
FIGURE 203. A SIMPLE ILLUSTRATION OF THE RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK
RxOHFrame
RxOH
RxOHClk
RxOHEnable
RReecceeiviveeOOvveerrhheeaadd
OOuutptpuuttIInnteterrfafaccee
BBlolocckk
From Receive
E3 Framer Block
The E3, ITU-T G.832 frame consists of 537 bytes. Of
these bytes, 530 bytes are payload bits and the re-
maining 7 bytes are overhead bytes. The XRT72L56
has been designed to handle and process both the
payload type and overhead type bytes for each E3
frame.
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