XRT72L56 Datasheet, PDF (264/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)
BIT 7
CP-Bit Error
Interrupt
Status
RUR
0
BIT 6
LOS
Interrupt
Status
RUR
0
BIT 5
AIS
Interrupt
Status
RUR
0
BIT 4
Idle Interrupt
Status
RUR
1
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
AIC
Interrupt
Status
RUR
0
BIT 1
OOF
Interrupt
Status
RUR
0
BIT 0
P-Bit Error
Interrupt
Status
RUR
0
Whenever the Terminal Equipment encounters the
Change in Idle Condition Receive Interrupt, it should
do the following.
1. It should determine the current state of the Idle
condition. Recall, that this interrupt can gener-
ated, whenever the XRT72L56 Framer declares
or clears the Idle condition. Hence, the user can
determine the current state of the Idle condition
by reading the state of Bit 5 (RxIdle), within the
RxDS3 Configuration & Status Registers, as illus-
trated below
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10)
BIT 7
RxAIS
RO
0
BIT 6
RxLOS
RO
0
BIT 5
RxIdle
RO
0
BIT 4
RxOOF
RO
0
BIT 3
Reserved
RO
0
BIT 2
Framing On
Parity
RO
0
BIT 1
FSync
Algo
RO
0
BIT 0
MSync
Algo
RUR
0
4.3.6.2.5 The Change of State of Receive FERF
Interrupt
If the Change of State on Receive FERF Interrupt is
enabled, then the XRT72L56 Framer IC will generate
an interrupt in response to either of the following con-
ditions.
1. When the XRT72L56 Framer IC detects the
FERF indicator, in the incoming DS3 data stream,
and
2. When the XRT72L56 Framer IC no longer detects
the FERF indicator, in the incoming DS3 data
stream.
Conditions causing the XRT72L56 Framer IC to
declare an FERF (Far-End-Receive Failure) condi-
tion
• If the Receive DS3 Framer block (within the
XRT72L56 Framer IC) detects some incoming DS3
frames with both of the “X” bits set to “0”.
Conditions causing the XRT72L56 Framer IC to
clear the FERF condition.
• Whenever, the Receive DS3 Framer block starts to
detect some incoming DS3 frames, in which the “X”
bits are not set to “0”.
Enabling and Disabling the Change of State on
Receive FERF Interrupt:
The user can enable or disable the Change of State
on Receive FERF Interrupt, by writing the appropriate
value into Bit 3 (FERF Interrupt Enable) within the
RxDS3 Interrupt Enable Register, as illustrated below.
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)
BIT 7
CP Bit Error
Interrupt
Enable
R/W
0
BIT 6
LOS
Interrupt
Enable
R/W
0
BIT 5
AIS
Interrupt
Enable
R/W
0
BIT 4
Idle Interrupt
Enable
R/W
0
BIT 3
FERF
Interrupt
Enable
R/W
0
BIT 2
AIC
Interrupt
Enable
R/W
0
BIT 1
OOF
Interrupt
Enable
R/W
0
BIT 0
P-Bit Error
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables this interrupt. Con- rupt.
versely, setting this bit-field to “0” disables this inter-
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