XRT72L56 Datasheet, PDF (435/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç
PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
When the Receive E3 Framer block clears the LOS
condition, then it will notify the Microprocessor and
the external circuitry of this occurrence by:
• Generating the Change in LOS Condition Interrupt
to the Microprocessor.
• Clearing Bit 4 (RxLOS) within the Rx E3 Configura-
tion & Status Register, as depicted below.
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Rx LOF Algo RxLOF
RxOOF
RxLOS
RxAIS RxPld Unstab
R/W
RO
RO
RO
RO
RO
0
0
0
1
0
0
BIT 1
Rx
TMark
RO
0
BIT 0
RxFERF
RO
0
• Clear the RxLOS output pin (e.g., toggle it "Low”).
6.3.2.6.2 The AIS (Alarm Indication Status)
Condition
Declaring the AIS Condition
The Receive E3 Framer block will identify and declare
an AIS condition, if it detects an “All Ones” pattern in
the incoming E3 data stream. More specifically, the
Receive E3 Framer block will declare an AIS Condi-
tion if 7 or less “0s” are detected in each of 2 consec-
utive E3 frames.
If the Receive E3 Framer block declares an AIS Con-
dition, then it will do the following.
• Generate the Change in AIS Condition Interrupt to
the Microprocessor. Hence, the Receive E3
Framer block will assert Bit 1 (AIS Interrupt Status)
within the Rx E3 Framer Interrupt Status register -
1, as depicted below.
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
COFA
Interrupt
Status
OOF
Interrupt
Status
LOF
Interrupt
Status
LOS
Interrupt
Status
AIS
Interrupt
Status
RO
RO
RO
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
1
• Assert the RxAIS output pin.
• Set Bit 3 (Rx AIS) within the Rx E3 Configuration &
Status Register, as depicted below.
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Rx LOF Algo RxLOF
RxOOF
RxLOS
RxAIS RxPld Unstab
R/W
RO
RO
RO
RO
RO
0
0
0
0
1
0
BIT 1
Rx
TMark
RO
0
BIT 0
RxFERF
RO
0
Clearing the AIS Condition
The Receive E3 Framer block will clear the AIS condi-
tion when it detects two consecutive E3 frames, with
eight or more “zeros” in the incoming data stream.
The Receive E3 Framer block will inform the Micro-
processor that the AIS Condition has been cleared
by:
• Generating the Change in AIS Condition Interrupt
to the Microprocessor. Hence, the Receive E3
Framer block will assert Bit 1 (AIS Interrupt Status)
416