XRT72L56 Datasheet, PDF (106/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
The local µP can determine the current state of the
AIS condition by reading bit 7 of the Rx E3 Configura-
tion and Status Register (Address = 0x11).
NOTE: For more information on the AIS Condition please
see Section 5.3.2.6.2.
2.4.3.6 Receive E3 Interrupt Status Register -
2 (E3, ITU-T G.832)
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
TTB
Change
Interrupt
Status
Not Used
FEBE
Interrupt
Status
FERF
Interrupt
Status
BIP-8
Error Interrupt
Status
Framing
Byte Error
Interrupt
Status
RxPld
Mis
Interrupt
Status
RO
RUR
RO
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Bit 6 - TTB Change Interrupt Status (Receipt of
New Trail Trace Buffer Message interrupt)
This Reset-upon-Read bit-field will be set to "1" if a
Receipt of New Trail Trace Buffer Message interrupt
has occurred since the last read of this register.
The Receive DS3/E3 Framer block will generate the
Receipt of New Trail Trace Buffer Message interrupt,
if it receives an E3 frame in which the value of the TR
byte-field is of the form "1xxxxxxxb". A TR byte-field
value of this form is identified as the frame start mark-
er.
NOTE: Please see Section 5.3.6.1.6 for a more detailed dis-
cussion of this interrupt.
Bit 4 - FEBE (Far-End Block Error) Interrupt Status
This Reset-upon-Read bit-field will be set to "1" if the
FEBE (Far-End-Block Error) interrupt has occurred
since the last read of this register.
The Receive DS3/E3 Framer block will generate the
FEBE interrupt anytime it detects a "1" in the FEBE
bit-field within an incoming E3 frame.
NOTE: Please see Section 5.3.6.1.8 for a more detailed dis-
cussion of this interrupt.
Bit 3 - FERF Interrupt Status
This Reset Upon Read bit will be set to '1' if the Re-
ceive E3 Framer has detected a Change in the Rx
FERF Condition, since the last time this register was
read.
This bit-field will be asserted under either of the fol-
lowing two conditions.
1. When the Receive DS3/E3 Framer block first
detects the occurrence of an RxFERF Condition
(e.g., when the FERF bit, within the last 3 or 5
consecutive E3 frames are set to "1").
2. When the Receive DS3/E3 Framer block detects
the end of the RxFERF Condition (e.g., when the
FERF bit, within the last 3 or 5 consecutive E3
frames are set to "0").
NOTE: For more information on the RxFERF (Yellow Alarm)
condition, please see Section 5.3.2.6.3.
Bit 2 - EM (BIP-8) Byte Error Interrupt Status
This Reset-upon-Read bit-field will be set to "1" if the
BIP-8 Error interrupt has occurred since the last read
of this register.
The Receive DS3/E3 Framer block will generate the
BIP-8 Error interrupt if it has concluded that it has re-
ceived an errored E3 frame, from the Remote Termi-
nal.
NOTE: Please see Section 5.3.6.1.9 for a more detailed dis-
cussion of this interrupt.
Bit 1 - Framing Byte Error Interrupt Status
This Reset-upon-Read bit-field will be set to "1" if the
Framing Byte Error interrupt has occurred since the
last read of this register.
The Receive DS3/E3 Framer block will generate the
Framing Byte Error interrupt if it has detected an error
in the FA1 or FA2 bytes, on an incoming E3 frame.
NOTE: Please see Section 5.3.6.1.10 for a more detailed
discussion of this interrupt.
Bit 0 - Rx Pld Mis Interrupt Status
This Reset-upon-Read bit-field will be set to "1" if the
Payload Type Mismatch interrupt has occurred since
the last read of this register.
The Receive DS3/E3 Framer block will generate the
Payload Type Mismatch interrupt when it detects that
the values, within the Payload Type bit-fields of the in-
coming E3 frame, has changed from that of the previ-
ous E3 frame.
NOTE: Please see Section 5.3.6.1.11 for a more detailed
discussion on this interrupt.
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