XRT72L56 Datasheet, PDF (101/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
RXE3 CONFIGURATION & STATUS REGISTER 1 (ADDRESS = 0X10)
BIT 7
BIT 6
RxPLDType[2:0]
BIT 5
BIT 4
RxFERF
Algo
BIT 3
RxTMark
Algo
BIT 2
RO
RO
RO
RO
RO
R/W
0
0
0
0
0
0
BIT 1
RxPLDExp[2:0]
R/W
0
BIT 0
R/W
0
Bit 7 - 5 - RxPLDType[2:0] (Received Payload
Type[2:0])
These three Read-Only bit-fields contain the Payload
Type value within the MA byte of the most recently re-
ceived E3 frame.
NOTES:
1. The Payload Type Mismatch interrupt will be gener-
ated if the contents of these bit-fields differ from
that of the Expected Payload Types in Bits 2
through 0 within this Register.
2. These bit-fields are ignored is the channel is config-
ured to support the October 1998 version of the
ITU-T G.832 framing format for E3.
Bit 4 - RxFERF Algo
This Read/Write bit-field allows the user to select one
of the two RxFERF Declaration Algorithms:
Writing a "0" to this bit-field selects the following
RxFERF Declaration algorithm:
• The Receive DS3/E3 Framer declares a Far End
Receive Failure (FERF) if the FERF bit-field, within
the MA byte is set to "1" for 3 consecutive incoming
E3 Frames. Likewise, the Receive DS3/E3 Framer
block will negate the Far End Receive Failure condi-
tion if the FERF bit-field, within the MA byte is set to
"0" for 3 consecutive incoming E3 Frames.
Writing a "1" to this bit-field selects the following
RxFERF Declaration algorithm:
• The Receive DS3/E3 Framer block declares a Far
End Receive Failure (FERF) if the FERF bit-field,
within the MA byte is set to "1" for 5 consecutive E3
Frames. Likewise, the Receive E3/DS3 Framer
block will negate the Far End Receive Failure condi-
tion if the FERF bit-field, within the MA byte is set to
"0" for 5 consecutive incoming E3 Frames.
Bit 3 - RxTMark Algorithm
This Read/Write bit-field allows the user to select the
number of consecutive incoming E3 frames, that the
Timing Marker bit-field (within the MA byte-field) must
be of a given logic state, before it is validated by the
Receive DS3/E3 Framer block. Once the Receive
DS3/E3 Framer block has validated the state of the
Timing Marker bit-field, then it will write this logic
state into Bit 1 (RxTMark) within the Rx E3 Configura-
tion & Status Register 2 (Address = 0x11)
Writing a "0" into this bit-field causes the Receive
DS3/E3 Framer block to validate the Timing Marker
value after receiving 3 consecutive incoming E3
frames, with the Timing Marker bit-field of a given val-
ue. Writing a "1" into this bit-field causes the Receive
DS3/E3 Framer block to validate the Timing Marker
value after receiving 5 consecutive incoming E3
frames, with the Timing Marker bit-field of a given val-
ue.
NOTE: This bit-field is ignored if the channel is configured
to support the October 1998 version of the ITU-T G.832
framing format for E3.
Bits 2 - 0: RxPLDExp[2:0]
This Read/Write bit-field allows the user to specify the
Payload Type that is expected in the MA bytes, of
each incoming E3 frame.
If the Receive DS3/E3 Framer detects a Payload Type
that differs from the values within these bit-fields, then
the Framer will generate the Payload Type Mismatch
interrupt.
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