XRT72L56 Datasheet, PDF (80/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
Address Bus into its internal circuitry. At this
point, the initial address of the burst access has
now been selected.
A.5 Further, the µC/µP should indicate that this
cycle is a Read cycle by setting the WR_R/W
(R/W*) input pin "High".
A.6 Next the µC/µP should initiate the current bus
cycle by toggling the RD_DS (Data Strobe)
input pin "Low". This step will enable the bi-
directional data bus output drivers, within the
XRT72L56 DS3/E3 Framer device. At this
point, the bi-directional data bus output drivers
will proceed to driver the contents of the
Address register onto the bi-directional data
bus.
A.7 After some settling time, the data on the bi-
directional data bus will stabilize and can be
read by the µC/µP. The XRT72L56 DS3/E3
Framer will indicate that this data can be read
by asserting the RDY_DTCK (DTACK) signal.
A.8 After the µC/µP detects the RDY_DTCK signal
(from the XRT72L56 DS3/E3 Framer) it will ter-
minate the Read Cycle by toggling the RD_DS
(Data Strobe) input pin "High".
Figure 33 presents an illustration of the behavior of
the Microprocessor Interface Signals during the initial
Read Operation, within a Burst I/O Cycle, for a Motor-
ola-type µC/µP.
FIGURE 33. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING THE INITIAL READ OPERATION OF A
BURST CYCLE (MOTOROLA TYPE PROCESSOR)
ALE_AS
A(11:0)
CS
D(7:0)
RD_DS
WR_R/W
RDY_DTCK
Address of "Initial" Target Register (Offset = 0x00)
Not Valid
Valid Data at
Offset = 0x00
At the completion of this initial read cycle, the µC/µP
has read in the contents of the first register or buffer
location (within the XRT72L56 DS3/E3 Framer) for
this particular burst access operation. In order to il-
lustrate how this burst I/O cycle works, the byte (or
word) of data, that is being read in Figure 33 has
been labeled Valid Data at Offset = 0x00. This indi-
cates that the µC/µP is reading the very first register
(or buffer location) in this burst access.
2.3.2.2.2.1.2 The Subsequent Read Operations
The procedure that the µC/µP must use to perform
the remaining read cycles, within this Burst Access
operation, is presented below.
B.0 Execute each subsequent Read Cycle, as
described in steps B.1 through B.3, below.
B.1 Without toggling the ALE_AS input pin (e.g.,
keeping it "High"), toggle the RD_DS (Data
Strobe) input pin "Low". This step accom-
plishes the following.
a. The Framer internally increments the latched
address value (within the Microprocessor Inter-
face circuitry).
b. The output drivers of the bi-directional data bus
(D[7:0]) are enabled. At some time later, the reg-
ister or buffer location corresponding to the incre-
mented latched address value will be driven onto
the bi-directional data bus.
NOTE: In order to insure that the XRT72L56 DS3/E3
Framer device will interpret this signal as being a Read sig-
nal, the µC/µP should keep the WR_R/W input pin "High".
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