XRT72L56 Datasheet, PDF (103/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
consecutive E3 frames, with the FERF bit-field (within
the MA byte) set to "1". This user-selectable number
is either 3 or 5 E3 frames. Conversely, the Receive
E3 Framer will negate the FERF declaration, if it has
received this user-selectable number of consecutive
E3 frames, with the FERF bit-field set to "0".
If this bit-field is set to "1", then the Receive DS3/E3
Framer block has declared an FERF condition. If this
bit-field is set to "0", then the Receive DS3/E3 Framer
block has not declared an FERF condition.
NOTE: Please see Section 5.1.1.4, for a more detailed dis-
cussion on the meaning of the FERF bit-field, within the E3
frame.
2.4.3.3 3.3.2.17 Receive E3 Interrupt Enable
Register (E3, ITU-T G.832)
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12)
BIT 7
Not Used
BIT 6
SSM MSG
Interrupt
Enable
BIT 5
SSM OOS
Interrupt
Enable
BIT 4
COFA
Interrupt
Enable
BIT 3
OOF
Interrupt
Enable
BIT 2
LOF
Interrupt
Enable
BIT 1
LOS
Interrupt
Enable
BIT 0
AIS
Interrupt
Enable
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 6 - SSM Message Interrupt Enable
This Read/Write bit-field permits the user to enable or
disable the Change in Synchronous Status Message
(SSM) interrupt. Setting this bit-field to “1” enables
this interrupt. Setting this bit-field to “0” disables this
interrupt.
NOTE: This bit-field is ignored if the Channel is configured
to support the November 1995 revision of the ITU-T G.832
Framing format for E3.
Bit 5 - SSM OOF (Out of Sequence) Interrupt En-
able
This Read/Write bit-field permits the user to enable or
disable the Change in SSM Out of Sequence State
interrupt. Setting this bit-field to “1” enables this inter-
rupt. Setting this bit-field to “0” disables this interrupt.
NOTE: This bit-field is ignored if the Channel is configured
to support the November 1995 revision of the ITU-T G.832
Framing format for E3.
Bit 4 - Change of Frame Alignment (COFA) Inter-
rupt Enable
This Read/Write bit-field allows the user to enable or
disable the Change of Frame Alignment interrupt.
Setting this bit-field to "1" enables this interrupt. Set-
ting this bit-field to "0" disables this interrupt.
Bit 3 - OOF (Out of Frame) Interrupt Enable
This Read/Write bit field allows the user to enable or
disable the Change in Out-of-Frame (OOF) status in-
terrupt. Setting this bit-field to "1" enables this inter-
rupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on the OOF Condition, please
see Section 5.3.2.1.
Bit 2 - LOF (Loss of Frame) Interrupt Enable
This Read/Write bit-field allows the user to enable or
disable the Change in Loss-of-Frame (LOF) status in-
terrupt. Setting this bit-field to "1" enables this inter-
rupt. Setting this bit-field to "0" disables this interrupt.
For more information on the LOF Condition, please
see Section 5.3.2.1.
Bit 1 - LOS (Loss of Signal) Interrupt Enable
This Read/Write bit-field allows the user to enable or
disable the Change in LOS condition interrupt. Set-
ting this bit-field to "1" enables this interrupt. Setting
this bit-field to "0" disables this interrupt.
NOTE: For more information on the LOS Condition, please
see Section 5.3.2.6.
Bit 0 - AIS Interrupt Enable
This Read/Write bit-field allows the user to enable or
disable the Change in AIS condition interrupt. Setting
this bit-field to "1" enables this interrupt. Setting this
bit-field to "0" disables this interrupt.
NOTE: For more information on the AIS Condition, please
see Section 5.3.2.6.2.
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