XRT72L56 Datasheet, PDF (136/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
This Read/Write byte-field, along with the Tx TTB-0
through Tx TTB-14 registers permit a user to define a
Trail Access Point Identifier sequence of bytes, that
will be transmitted to the Remote Terminal. The Re-
mote Receiving Terminal will use this sequence of
bytes to verify that it is connected to the proper Trans-
mitting Terminal. The Transmit DS3/E3 Framer block
will take the contents of these 16 registers, and insert
them into the TR byte of the outbound E3 frame. In
the sixteenth of a set of 16 E3 Frames, the Transmit
DS3/E3 Framer block will read in the contents of this
register, and insert it into the TR byte-field, within the
very next outbound E3 frame.
The contents of this register, along with Tx TTB-1
through Tx TTB-15 are used to transmit 15 ASCII
characters required for the E.164 numbering format.
2.4.6.23 Transmit E3 FA1 Byte Error Mask Reg-
ister (E3, ITU-T G.832)
TXE3 FA1 ERROR MASK REGISTER (ADDRESS = 0X48)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxFA1_Error_Mask_Byte[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
This Read/Write bit-field permits the user to insert er-
rors into the Framing Alignment octet, FA1 of each
outbound E3 frame. The user may wish to do this for
equipment testing purposes. Prior to transmission,
the Transmit DS3/E3 Framer block reads in the FA1
byte, and performs an XOR operation with it and the
contents of this register. The results of this operation
are written back into the FA1 octet position, in each
outbound E3 frame. Consequently, to insure errors
are not injected into the FA1 octet of the outbound E3
frames, the contents of this register must be set to all
“0’s” (the default value).
2.4.6.24 Transmit E3 FA2 Byte Error Mask Reg-
ister (E3, ITU-T G.832)
TXE3 FA2 ERROR MASK REGISTER (ADDRESS = 0X49)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
TxFA2_Error_Mask_Byte[7:0]
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
R/W
0
BIT 1
R/W
0
BIT 0
R/W
0
This Read/Write bit-field permits the user to insert er-
rors into the Framing Alignment octet, FA2 of each
outbound E3 frame. The user may wish to do this for
equipment testing purposes. Prior to transmission,
the Transmit DS3/E3 Framer block reads in the FA2
byte, and performs an XOR operation with it and the
contents of this register. The results of this operation
are written back into the FA2 octet position, in each
outbound E3 frame. Consequently, to insure errors
are not injected into the FA2 octet of the outbound E3
frames, the contents of this register must be set to all
"0’s" (the default value).
2.4.6.25 Transmit E3 BIP-8 Error Mask Register
(E3, ITU-T G.832)
TXE3 BIP-8 ERROR MASK REGISTER (ADDRESS = 0X4A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
TxBIP-8_Error_Mask_Byte[7:0]
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
R/W
0
BIT 1
R/W
0
BIT 0
R/W
0
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