XRT72L56 Datasheet, PDF (52/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
áç
PRELIMINARY
AC ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: TA = 25(C, VCC = 3.3V + 5% unless otherwise specified
SYMBOL
PARAMETER
MIN. TYP.
MAX. UNITS
CONDITIONS
t₃₉ "RxPOS" or "RxNEG" hold time, from rising edge of
5
ns
"RxLineClk"
(Framer is configured to sample data on "RxPOS"
and "RxNEG" input pins, on the rising edge of "RxLi-
neClk")
t₄₀ "RxPOS" or "RxNEG" set-up time to falling edge of
3
ns
"RxLineClk".
(Framer is configured to sample data on "RxPOS"
and "RxNEG" input pins, on the falling edge of "RxLi-
neClk")
t₄₁ "RxPOS" or "RxNEG" hold time, from falling edge of 5
ns
"RxLineClk"
(Framer is configured to sample data on "RxPOS"
and "RxNEG" input pins, on the falling edge of "RxLi-
neClk")
Receive Payload Data Output Inteface Timing - Serial Mode Operation (See Figure 13)
t₅₀ Rising edge of RxClk to "Payload Data" (RxSer) out- 10
11
12
ns
put delay
13
14
15
DS3 Applications
E3 Applications
t₅₁ Rising edge of "RxClk" to "RxFrame" output delay
10
11
12
ns DS3 Applications
13
14
15
E3 Applications
t₅₂ Rising edge of "RxClk" to "RxOHInd" output delay.
10
11
12
ns DS3 Applications
13
14
15
E3 Applications
Receive Payload Data Output Interface Timing - Nibble Mode Operation (see Figure 14)
t₅₃
Falling edge of “RxClk” to rising edge of “RxFrame”
output delay
2
ns
t₅₄
Falling edge of “RxClk” to rising edge of “RxNib[3:0]”
output delay
1
ns
Receive Overhead Data Output Interface Timing - Method 1 - Using RxOHEnable (see Figure 15)
t_59A ^{Falling edge of “RxOHClk” to “RxFrame” output}
20
25
ns DS3 Applications
25
t_59B ^{Falling edge of “RxClk” to “RxOH” output delay}
20
28
E3 Applications
25
ns DS3 Applications
25
28
E3 Applications
Receive Overheadf Data Output Interface Timing - Method 2 - Using RxOHEnable (see Figure 16)
t₆₀ Rising edge of "RxOutClk" to rising edge of
2
"RxOHEnable" delay.
7
ns
33