XRT72L56 Datasheet, PDF (231/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
incoming 0s via the RxPOS and RxNEG input pins or
if the RLOS input pin (from the XRT7300 DS3 LIU or
the XRT7295 Line Receiver IC) is asserted (e.g., driv-
en "High"). The Receive DS3 Framer block will indi-
cate the occurrence of an LOS condition by:
1. Asserting the RxLOS output pin (e.g., toggles it
"High").
2. Setting Bit 6 (RxLOS) within the Rx DS3 Configu-
ration and Status Register to 1, as depicted
below.
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
RxAIS
R/O
0
RxLOS
R/O
1
RxIdle
R/O
0
RxOOF
R/O
1
Int LOS
Disable
R/W
x
Framing on
Parity
R/W
x
F-Sync Algo M-Sync Algo
R/W
R/W
x
x
3. The Receive DS3 Framer block will generate a
Change in LOS Status interrupt request.
NOTE: The Receive DS3 Framer will also declare an OOF
condition and perform all of the notification procedures as
described in Section 3.3.2.2.
4. Force the on-chip Transmit Section to transmit a
FERF (Far-End Receive Failure) indicator back
out to the remote terminal.
The Receive DS3 Framer block will clear the LOS
condition when at least 60 out of 180 consecutive re-
ceived bits are 1.
NOTE: The Receive DS3 Framer block will also generate
the Change in LOS Condition interrupt, when it clears the
LOS Condition.
The Framer chip allows the user to modify the LOS
Declaration criteria such that an LOS condition is de-
clared only if the RLOS input pin (from the XRT7300
DS3/E3/STS-1 LIU IC) is asserted. In this case, the
internally-generated LOS criteria of 180 consecutive
0s will be disabled. The user can accomplish this by
writing a "1" to bit 3 (Int LOS Disable) of the Rx DS3
Configuration and Status Register, as depicted below.
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10)
BIT 7
RxAIS
BIT 6
RxLOS
BIT 5
RxIdle
BIT 4
RxOOF
RO
RO
RO
RO
X
X
X
X
NOTE: For more information on the RLOS input pin, please
see Section 2.1.
4.3.2.5.2 The Alarm Indication Signal (AIS)
The Receive DS3 Framer block will identify and de-
clare an AIS condition if it detects all of the following
conditions in the incoming DS3 Data Stream:
• Valid M-bits, F-bits and P-bits
• All C-bits are zeros.
• X-bits are set to 1
• The Payload portion of the DS3 Frame exhibits a
repeating 1010... pattern.
The Receive DS3 Framer block contains, within its
circuitry, an Up/Down Counter that supports the as-
sertion and negation of the AIS condition. This
counter begins with the value of 0x00 upon power up
or reset. The counter is then incremented anytime
the Receive DS3 Framer block detects an AIS Type
M-frame. This counter is then decremented, or kept
at zero value, when the Receive DS3 Framer block
BIT 3
BIT2
BIT 1
BIT 0
Int LOS
Disable
R/W
1
Framing on
Parity
R/W
X
F-Sync Algo M-Sync Algo
R/W
R/W
X
X
detects a non-AIS type M-frame. The Receive DS3
Framer block will declare an AIS Condition if this
counter reaches the value of 63 M-frames or greater.
Explained another way, the AIS condition is declared
if the number of AIS-type M-frames is detected, such
that it meets the following conditions:
NAIS - NVALID > 63
where:
NAIS = the number of M-frames containing the AIS
pattern.
NVALID = the number of M-frames not containing the
AIS pattern
If at anytime, the contents of this Up/Down counter
exceeds 63 M-frames, then the Receive DS3 Framer
block will:
1. Assert the RxAIS output pin by toggling it "High".
2. Set Bit 7 (RxAIS) within the Rx DS3 Configuration
and Status Register, to "1" as depicted below.
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