XRT72L56 Datasheet, PDF (151/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
nate) the current Read or Write cycle with the Framer
Microprocessor Interface section.
The user may enable or disable this LOC Protection
feature by writing to Bit 7 (LOC Enable) within the
Framer I/O Register, as depicted below.
ADDRESS = 0X01, FRAMER I/O CONTROL REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
LOC Enable Test PMON
Interrupt
Enable
Reset
AMI/B3ZS*
Unipolar/
Bipolar*
R/W
R/W
R/W
R/W
R/W
1
0
1
0
0
BIT 2
TxLine
Clk Inv
R/W
0
BIT 1
RxLine
Clk Inv
R/W
0
BIT 0
Reframe
R/W
0
Writing a "1" to this bit-field enables this LOC Protec-
tion feature. Writing a "0" to this bit-field disables this
feature.
NOTE: The Ring Oscillator can be a source of noise, within
the Framer chip. Hence, there may be situations where the
user will wish to disable the LOC Protection feature.
2.6 USING THE PMON HOLDING REGISTER
The Microprocessor Interface section consists of an
8-bit bi-directional data bus. As a consequence, the
local µP will be able to read from and write to the
Framer on-chip registers, 8 bit per (read or write) cy-
cle. Since most of the Framer on-chip registers con-
tain 8-bits, communicating with the local µP, over an
8-bit data bus, is not much of an inconvenience.
However, all of the PMON registers, within the Framer
IC, contain 16 bits. Consequently, any reads of the
PMON registers, will require two read cycles. To
make matters potentially more complicated, these
PMON registers are “Reset-upon-Read” registers.
Therefore, the contents of both the “MSB” and “LSB”
registers (of the “READ” PMON register) are reset to
zero upon the first of these two read cycles.
Fortunately, the XRT72L56 Framer IC includes a fea-
ture that will make reading a PMON register a slightly
less complicated task. The Framer chip address
space contains a “read-only” register known as the
PMON Holding register, which is located at 0x6C.
Whenever the local µP reads in an 8-bit value of a
given PMON registers (e.g., either the upper-byte or
the lower byte value of the PMON register), the other
8-bit value of that PMON register will automatically be
loaded into the PMON Holding register. As a conse-
quence, the other 8-bit value of the PMON register is
accessible by reading the PMON Holding register.
Hence, anytime the local µP is trying to read in the
contents of a PMON register, the first read access
must be made directly to one of the 8-bit values of the
PMON registers (e.g., for example: the PMON LCV
Event Count Register - MSB, Address = 0x50). How-
ever, the second read must always be made to a con-
stant location in system memory, the PMON Holding
Register.
2.7 THE INTERRUPT STRUCTURE WITHIN THE FRAMER
MICROPROCESSOR INTERFACE SECTION
The XRT72L56 Framer device is equipped with a so-
phisticated Interrupt Servicing Structure. This Inter-
rupt Structure includes an Interrupt Request output,
INT, numerous Interrupt Enable Registers and numer-
ous Interrupt Status Registers. The Interrupt Servic-
ing Structure, within each of the three channels con-
tains two levels of hierarchy. The top level is at the
functional block level (e.g., the Receive Section, the
Transmit Section, etc.). The lower hierarchical level is
at the individual interrupt or source level. Each hier-
archical level consists of a complete set of Interrupt
Status Registers/bits and Interrupt Enable Registers/
bits, as will be discussed below.
Both of the functional sections, within each channel,
are capable of generating Interrupt Requests to the
local µP/µC. The Framer device Interrupt Structure
has been carefully designed to allow the user to
quickly determine the exact source of the interrupt
(with minimal latency) which will aid the local µP/µC in
determining which interrupt service routine to call up
in order to respond to or eliminate the condition(s)
causing the interrupt.
Table 6 lists all of the possible conditions that can
generate interrupts, with each functional section of a
given channel.
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