XRT72L56 Datasheet, PDF (36/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
PIN DESCRIPTION FOR THE XRT72L56
PIN #
J25
J26
K1
K2
K3
K4
K23
PIN NAME
RDY_DTCK
D(6)
TxPOS[5]
TxLineClk[5]
RxOutClk[0]/
RxHDLCDat7[0]
TxNEG[0]
D(7)
TYPE
O
I/O
O
O
O
O
I/O
DESCRIPTION
READY or DTACK:
This active-low output pin will function as the READY output, when the
microprocessor interface is running in the "Intel" Mode; and will function as
the DTACK output, when the microprocessor interface is running in the
"Motorola" Mode.
"Intel" Mode - READY Output:
When the Framer negates this output pin (e.g., toggles it "low"), it indicates
(to the µP) that the current READ or WRITE cycle is to be extended until
this signal is asserted (e.g., toggled "high").
"Motorola" Mode - DTACK (Data Transfer Acknowledge) Output:
The Framer device will assert this pin in order to inform the local micropro-
cessor that the present READ or WRITE cycle is nearly complete. If the
Framer device requires that the current READ or WRITE cycle be extended,
then the Framer will delay its assertion of this signal. The 68000 family of
µPs requires this signal from its peripheral devices, in order to quickly and
properly complete a READ or WRITE cycle.
See Description for Pin K23
See Description for Pin J1
See Description for Pin J2
Receive Out Clock - Transmit Terminal Interface Clock for Loop-Tim-
ing:
This clock signal functions as the "Terminal Interface" clock source, if the
XRT72l56 Framer IC is operating in the "loop-timing" mode.
In this mode, the Transmitting Terminal Equipment is expected to input data
to the Framer IC, via the “TxSer” input pin, upon the rising edge of this clock
signal. The XRT72l56 device will use the rising edge of this clock signal to
sample the data at the TxSer input.
This clock signal is a buffered version of the RxLineClk signal.
Receive HDLC Data Output - 7:
This pin contains bit 7 RxHDLC data when the HDLC controller is turned on.
Transmit Negative Polarity Pulse:
The exact role of this output pin depends upon whether the Framer is oper-
ating in the Unipolar or Bipolar Mode.
Unipolar Mode:
This output signal pulses "high" for one bit period, at the end of each "out-
bound" DS3 or E3 frame. This output signal is at a logic "low" for all of the
remaining bit-periods of the "outbound" DS3 or E3 frames
Bipolar Mode:
This output pin functions as one of the two dual-rail output signals that com-
mands the sequence of pulses to be driven on the line. TxPOS is the other
output pin. This input is typically connected to the TNDATA input of the
external DS3/E3 Line Interface Unit IC. When this output is asserted, it will
command the LIU to generate a negative polarity pulse on the line.
MSB of Bi-Directional Data Bus (Microprocessor Interface Section):
This pin, along with pins D0 - D6, function as the Microprocessor Interface
bi-directional data bus, and is intended to be interfaced to the "local" micro-
processor.
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