XRT72L56 Datasheet, PDF (70/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
Byte). When an 8-bit PMON Register is concatenat-
ed with its companion 8-bit PMON Register, one ob-
tains the full 16-bit expression within that PMON Reg-
ister.
The consequence of having these 16-bit registers is
that an 8-bit µC/µP will have to perform two consecu-
tive read operations in order to read in the full 16-bit
expression contained within a given PMON register.
To complicate matters, these PMON Registers are
Reset-Upon-Read registers. More specifically, these
PMON Register are Reset-Upon-Read in the sense
that, the entire 16-bit contents, within a given PMON
Register is reset, as soon as an 8-bit µC/µP reads in
either byte of this two-byte (e.g., 16 bit) expression.
For example;
Consider that an 8-bit µC/µP needs to read in the
PMON LCV Event Count Register. In order to ac-
complish this task, the 8-bit µC/µP is going to have to
read in the contents of PMON LCV Event Count Reg-
ister - MSB (located at Address = 0x50) and the con-
tents of the PMON LCV Event Count Register - LSB
(located at Address = 0x51). These two eight-bit reg-
isters, when concatenated together, make up the
PMON LCV Event Count Register.
If the 8-bit µC/µP reads in the PMON LCV Event
Count-LSB register first, then the entire PMON LCV
Event Count register will be reset to 0x0000. As a
consequence, if the 8-bit µC/µP attempts to read in
the PMON LCV Event Count-MSB register in the very
next read cycle, it will read in the value 0x00.
The PMON Holding Register
In order to resolve this Reset-Upon-Read problem,
the XRT72L56 DS3/E3 Framer device includes a spe-
cial register, which permits 8-bit µC/µP to read in the
full 16-bit contents of these PMON registers. This
special register is called the PMON Holding Register
and is located at 0x6c within the Framer Address
space.
The operation of the PMON Holding register is as fol-
lows. Whenever an 8-bit µC/µP reads in one of the
bytes (of the 2-byte PMON register), the contents of
the unread (e.g., other) byte will be stored in the
PMON Holding Register. Therefore, the 8-bit µC/µP
must then read in the contents of the PMON Holding
Register in the very next read operation.
In Summary: Whenever an 8-bit µC/µP needs to
read a PMON Register, it must execute the follow-
ing steps.
Step 1: Read in the contents of a given 8-bit PMON
Register (it does not matter whether the µC/µP reads
in the MSB or the LSB register).
Step 2: Read in the contents of the PMON Holding
Register (located at Address = 0x6c). This register
will contain the contents of the other byte.
2.3.2 Data Access Modes
As mentioned earlier, the Microprocessor Interface
block supports data transfer between the Framer and
the µC/µP (e.g., Read and Write operations) via two
modes: the Programmed I/O and the Burst Modes.
Each of these Data Access Modes are discussed in
detail below.
2.3.2.1 Data Access using Programmed I/O
Programmed I/O is the conventional manner in which
a microprocessor exchanges data with a peripheral
device. However, it is also the slowest method of data
exchange between the Framer and the µC/µP.
The next two sections present detailed information on
Programmed I/O Access, when the XRT72L56 DS3/
E3 Framer is operating in the Intel Mode or in the Mo-
torola Mode.
2.3.2.1.1 Programmed I/O Access in the Intel
Mode
If the XRT72L56 DS3/E3 Framer is interfaced to an
Intel-type µC/µP (e.g., the 80x86 family, etc.), then it
should be configured to operate in the Intel mode (by
tying the MOTO pin to ground). Intel-type Read and
Write operations are described below.
2.3.2.1.1.1 The Intel Mode Read Cycle
Whenever an Intel-type µC/µP wishes to read the
contents of a register or some location within the Re-
ceive LAPD Message buffer or the Receive OAM Cell
Buffer, (within the Framer device), it should do the fol-
lowing.
1. Place the address of the target register or buffer
location (within the Framer) on the Address Bus
input pins A[11:0].
2. While the µC/µP is placing this address value on
the Address Bus, the Address Decoding circuitry
(within the user's system) should assert the CS
(Chip Select) pin of the Framer, by toggling it
"Low". This action enables further communica-
tion between the µC/µP and the Framer Micropro-
cessor Interface block.
3. Toggle the ALE_AS (Address Latch Enable) input
pin "High". This step enables the Address Bus
input drivers, within the Microprocessor Interface
block of the Framer.
4. After allowing the data on the Address Bus pins
to settle (by waiting the appropriate Address Data
Setup time), the µC/µP should toggle the
ALE_AS pin "Low". This step causes the Framer
device to latch the contents of the Address Bus
into its internal circuitry. At this point, the address
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