XRT72L56 Datasheet, PDF (96/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
2.4.2.11 Receive DS3 Interrupt Status Register
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
CP-Bit Error
Interrupt
Status
LOS
Interrupt
Status
AIS
Interrupt
Status
Idle Interrupt
Status
FERF
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
AIC
Interrupt
Status
RUR
0
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PRELIMINARY
BIT 1
OOF
Interrupt
Status
RUR
0
BIT 0
P-Bit Error
Interrupt
Status
RUR
0
Bit 7 - CP Bit Error Interrupt Status
This Reset-upon-Read bit-field indicates whether or
not the Detection of CP Bit Error Interrupt has oc-
curred since the last read of this register. This bit-
field will be “0” if the Detection of CP-Bit Error Inter-
rupt has not occurred since the last read of this regis-
ter. Conversely, this bit-field will be set to “1” if this in-
terrupt has occurred since the last read of this regis-
ter. The Detection of CP Bit Error Interrupt will occur
if the Receive DS3/E3 Framer block detects a CP bit-
error in the incoming DS3 frame.
NOTE: This bit-field is only valid if the channel has been
configured to operate in the DS3, C-bit Parity Framing for-
mat.
Bit 6 - LOS Interrupt Status
This Reset Upon Read bit will be set to "1", if the Re-
ceive DS3/E3 Framer block has detected a Change in
the LOS Status condition, since the last time this reg-
ister was read. This bit-field will be asserted under ei-
ther of the following conditions:
For DS3 Applications
1. When the Receive DS3/E3 Framer block detects
the occurrence of an LOS Condition (e.g., the
occurrence of 180 consecutive spaces in the
incoming DS3 data stream), and
2. When the Receive DS3/E3 Framer block detects
the end of an LOS Condition (e.g., when the
Receive DS3 Framer detects 60 mark pulses in
the last 180 bit periods).
For E3 Applications
3. When the Receive DS3/E3 Framer block detects
the occurrence of an LOS Condition (e.g., the
occurrence of 32 consecutive spaces in the
incoming E3 data stream).
4. When the Receive DS3/E3 Framer block detects
the end of an LOS Condition (e.g., the occur-
rence of 32 consecutive bits that does not contain
a string of 4 consecutive “0s”.
The local µP can determine the current state of the
LOS condition by reading bit 6 of the Rx DS3 Config-
uration and Status Register (Address = 0x10).
NOTE: For more information in the LOS of Signal (LOS)
Alarm, please see Section 3.3.2.5.1.
Bit 5 - AIS Interrupt Status
This Reset Upon Read bit field will be set to "1", if the
Receive DS3/E3 Framer block has detected a
Change in the AIS condition, since the last time this
register was read. This bit-field will be asserted un-
der either of the following two conditions:
1. When the Receive DS3/E3 Framer block first
detects an AIS Condition in the incoming DS3
data stream, and
2. When the Receive DS3/E3 Framer block has
detected the end of an AIS Condition.
The local µP can determine the current state of the
AIS condition by reading bit 7 of the Rx DS3 Configu-
ration and Status Register (Address = 0x10).
NOTE: For more information on the AIS Condition please
see Sections 3.3.2.5.2.
Bit 4 - Idle Interrupt Status
This Reset Upon Read bit-field is set to "1" when the
Receive DS3/E3 Framer block detects a Change in
the Idle Condition in the incoming DS3 data stream.
Specifically, the Receive DS3/E3 Framer block will as-
sert this bit-field under either of the following two con-
ditions:
1. When the Receive DS3/E3 Framer block detects
the onset of the Idle Condition and
2. When the Receive DS3/E3 Framer block detects
the end of the Idle Condition.
The local µP can determine the current state of the
Idle condition by reading bit 5 of the Rx DS3 Configu-
ration and Status Register (Address = 0x10).
NOTE: For more information into the Idle Condition, please
see Section 3.3.2.5.3.
Bit 3 - FERF Interrupt Status
This Reset Upon Read bit will be set to '1' if the Re-
ceive DS3/E3 Framer block has detected a Change in
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