XRT72L56 Datasheet, PDF (479/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
8.0 HIGH SPEED HDLC CONTROLLER MODE
OF OPERATION
Each channel, within the XRT72L56 device can be
configured to operate in the High-Speed HDLC Con-
troller Mode. Whenever a given channel is configured
to operate in this mode then the following will happen.
1. The Transmit Section of the channel will be con-
figured to accept outbound data (from the user’s
Terminal Equipment) via an 8-bit wide input inter-
face labeled TxHDLCDat_n[7:0]. The Transmit
Section of the channel will then encapsulate all
data, that it receives via TxHDLCDat_n[7:0].
2. The Transmit Section of the channel will then
encapsulate all data, that it receives via the
TxHDLCDat_n[7:0] interface, into HDLC frames.
These HDLC frames are variable-length packets
and are transported to the remote terminal equip-
ment via the outbound DS3 or E3 payload data
bits.
3. As the Transmit Section accepts and processes
data from the user’s terminal equipment, then it
will perform all of the necessary “0” stuffing into
the outbound HDLC frame, in order to prevent the
user-supplied data from mimicking either the flag
sequence octet (0x7E) or the ABORT sequence.
4. The Transmit Section can also be configured to
compute and append either a 16-bit or 32-bit
CRC value to the end of this “0” stuffed user’s
data, as a trailer.
5. Whenever the Transmit Section has no user data
to send to the remote terminal equipment (via
HDLC frames) then it will transmit a continuous
stream of flag sequence octets (0x7E) via the
DS3 or E3 payload bits.
6. The Receive Section of the channel will be con-
figured to receive and extract out these HDLC
frames via the inbound DS3/E3 data stream. The
Receive Section will then output the contents of
these received HDLC frames in a byte-wide man-
ner via the RxHDLCDat_n[7:0] output pins.
7. If the Receive Section of the channel is only
receiving a stream of flag sequences (0x7E) then
it will terminate this data stream and will not out-
put any data via the RxHDLCDat_n[7:0] output
pins.
8. As the Receive Section of the channel receives
these HDLC frames, it will also do the following.
• Compute and verify the 16-bit or 32-bit CRC value
(which has been appended to the HDLC frame, as
a trailer).
• Perform the necessary “0” un-stuffing in order to
restore the original content of the user-supplied
data.
8.1 CONFIGURING THE CHANNEL TO OPERATE IN THE
HIGH SPEED HDLC CONTROLLER MODE
The user can configure a given channel to operate in
the High Speed HDLC Controller Mode by writing the
appropriate data into the Channel’s HDLC Control
Register.
The address location of the HDLC Control register, for
each of the three channels (within the XRT72L56 de-
vice) is listed below in Table 93 .
TABLE 93: ADDRESS LOCATIONS OF EACH OF THE
HDLC CONTROL REGISTERS WITHIN THE
XRT72L56 DEVICE.
CHANNEL NUMBER
0
1
2
ADDRESS LOCATION
0x82
0x282
0x482
The user can configure a given channel to operate in
the High-Speed HDLC Controller Mode by setting bit
6 (HDLC ON), within the appropriate HDLC Control
Register to “1”, as depicted below.
HDLC CONTROL REGISTER (ADDRESS = 0X82)
BIT 7
Framer
By-Pass
R/W
0
BIT 6
HDLC
ON
R/W
1
BIT 5
CRC-32
Select
R/W
0
BIT 4
Reserved
R/W
0
8.2 OPERATING THE HIGH SPEED HDLC CONTROL-
LER
Once the user has configured a given channel to op-
erate in the High-Speed HDLC Controller Mode, then
both the Transmit and Receive HDLC Controller
BIT 3
HDLC
Loop-Back
R/W
0
BIT 2
R/W
0
BIT 1
Reserved
R/W
0
BIT 0
R/W
0
blocks, within the appropriate channel will be active.
The next few sections describe how to use the Trans-
mit and Receive HDLC Controller blocks, within a giv-
en channel.
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