XRT72L56 Datasheet, PDF (71/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
of the register or buffer locations (within the
Framer), has now been selected.
5. Next, the µC/µP should indicate that this current
bus cycle is a Read Operation by toggling the
RD_DS (Read Strobe) input pin "Low". This
action also enables the bi-directional data bus
output drivers of the Framer device. At this point,
the bi-directional data bus output drivers will pro-
ceed to drive the contents of the latched
addressed register (or buffer location) onto the bi-
directional data bus, D[7:0].
6. Immediately after the µC/µP toggles the Read
Strobe signal "Low", the Framer device will toggle
the RDY_DTCK output pin "Low". The Framer
device does this in order to inform the µC/µP that
the data (to be read from the data bus) is NOT
READY to be latched into the µC/µP.
7. After some settling time, the data on the bi-direc-
tional data bus will stabilize and can be read by
the µC/µP. The XRT72L56 DS3/E3 Framer will
indicate that this data can be read by toggling the
RDY_DTCK (READY) signal "High".
8. After the µC/µP detects the RDY_DTCK signal
(from the XRT72L56 DS3/E3 Framer), it can then
terminate the Read Cycle by toggling the RD_DS
(Read Strobe) input pin "High".
Figure 25 presents a timing diagram which illustrates
the behavior of the Microprocessor Interface signals,
during an Intel-type Programmed I/O Read Opera-
tion.
FIGURE 25. BEHAVIOR OF MICROPROCESSOR INTERFACE SIGNALS DURING AN INTEL-TYPE PROGRAMMED I/O READ
OPERATION
ALE_AS
A(11:0)
CS
D(7:0)
RD_DS
WR_R/W
RDY_DTCK
Address of target Register
Not Valid
Valid
2.3.2.1.1.2 The Intel Mode Write Cycle
Whenever an Intel-type µC/µP wishes to write a byte
or word of data into a register or buffer location, within
the Framer, it should do the following.
1. Assert the ALE_AS (Address Latch Enable) input
pin by toggling it "High". When the µC/µP asserts
the ALE_AS input pin, it enables the Address Bus
Input Drivers within the Framer chip.
2. Place the address of the target register or buffer
location (within the Framer), on the Address Bus
input pins, A[11:0].
3. While the µC/µP is placing this address value
onto the Address Bus, the Address Decoding cir-
cuitry (within the user's system) should assert the
CS input pin of the Framer device by toggling it
"Low". This step enables further communication
between the µC/µP and the Framer Microproces-
sor Interface block.
4. After allowing the data on the Address Bus pins
to settle (by waiting the appropriate Address
Setup time), the µC/µP should toggle the
ALE_AS input pin "Low". This step causes the
Framer device to latch the contents of the
Address Bus into its internal circuitry. At this
point, the address of the register or buffer location
(within the Framer), has now been selected.
5. Next, the µC/µP should indicate that this current
bus cycle is a Write Operation by toggling the
WR_R/W (Write Strobe) input pin "Low". This
action also enables the bi-directional data bus
input drivers of the Framer device.
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