XRT72L56 Datasheet, PDF (282/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
áç
PRELIMINARY
NOTE: In this case, the XRT72L56 dictates exactly when
the very next E3 frame will be generated. The Terminal
Equipment is expected to respond appropriately by provid-
ing the XRT72L56 with the first bit of the new E3 frame,
upon demand. Hence, in this mode, the XRT72L56 is
referred to as the Frame Master and the Terminal Equip-
ment is referred to as the Frame Slave.
Finally, the XRT72L56 will pulse its TxOH_Ind output
pin, one bit-period prior to it processing a given over-
head bit, within the outbound E3 frame. Since the
TxOH_Ind output pin (of the XRT72L56) is electrically
connected to the E3_Overhead_Ind whenever the
XRT72L56 pulses the TxOH_Ind output pin "High”, it
will also be driving the E3_Overhead_Ind input pin (of
the Terminal Equipment) "High". Whenever the Ter-
minal Equipment detects this pin toggling "High", it
should delay transmission of the very next DS3 frame
payload bit by one clock cycle.
The behavior of the signal between the XRT72L56
and the Terminal Equipment for E3 Mode 3 Operation
is illustrated in Figure 105.
FIGURE 105. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT72L56 AND THE TERMINAL
EQUIPMENT (E3 MODE 3 OPERATION)
Terminal Equipment Signals
E3_Clock_In
E3_Data_Out
Tx_Start_of_Frame
E3_Overhead_Ind
Payload[1522] Payload[1523]
FAS , Bit 9
FAS, Bit 8
XRT72L5x Transmit Payload Data I/F Signals
TxInClk
TxSer
Payload[1522] Payload[1523]
TxFrame
TxOH_Ind
FAS, Bit 9
FAS, Bit 8
E3 Frame Number N
Note: TxFrame pulses high to denote
E3 Frame Boundary.
Note: TxOH_Ind pulses high for 12
bit-periods in order to denote
Overhead Data (e.g., the FAS pattern,
the A and N bits).
E3 Frame Number N + 1
Note: FAS pattern will not be processed by the
Transmit Payload Data Input Interface.
How to configure the XRT72L56 to operate in this
mode.
1. Set the NibIntf input pin "Low".
2. Set the TimRefSel[1:0] bit-fields (within the
Framer Operating Mode Register) to "01" as
depicted below.
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Local
Loopback
DS3/E3*
R/W
R/W
0
0
Internal
LOS
Enable
R/W
1
RESET
R/W
0
Interrupt
Enable
Reset
R/W
1
Frame
Format
R/W
0
TimRefSel[1:0]
R/W
R/W
0
0
263