XRT72L56 Datasheet, PDF (78/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
during the initial write operation within a Burst Ac-
cess, for an Intel-type µC/µP.
FIGURE 31. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING THE INITIAL WRITE OPERATION OF
A BURST CYCLE (INTEL-TYPE PROCESSOR)
ALE_AS
A(11:0)
CS
D(7:0)
RD_DS
WR_R/W
RDY_DTCK
Address of "Initial" Target Register (Offset = 0x00)
Data to be Written
(Offset = 0x00)
At the completion of this initial write cycle, the µC/µP
has written a byte or word into the first register or
buffer location (within the XRT72L56 DS3/E3 Framer)
for this particular burst access operation. In order to
illustrate this point, the byte (or word) of data, that is
being written in Figure 31 has been labeled Data to
be Written (Offset = 0x00).
2.3.2.2.1.2.2 The Subsequent Write Operations
The procedure that the µC/µP must use to perform
the remaining write cycles, within this burst access
operation, is presented below.
B.0 Execute each subsequent write cycle, as
described in steps B.1 through B.3.
B.1 Without toggling the ALE_AS input pin (e.g.,
keeping it "Low"), apply the value of the next
byte or word (to be written into the Framer) to
the bi-directional data bus pins, D[7:0].
B.2 Toggle the WR_R/W (Write Strobe) input pin
"Low". This step accomplishes two things.
a. It enables the input drivers of the bi-directional
data bus.
b. It causes the Framer to internally increment the
value of the latched address.
B.3 After waiting the appropriate amount of settling
time the data, in the internal data bus, will stabi-
lize and is ready to be latched into the Framer
Microprocessor Interface block. At this point,
the µC/µP should latch the data into the Framer
by toggling the WR_R/W input pin "High".
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