XRT72L56 Datasheet, PDF (377/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
FIGURE 157. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA
INPUT INTERFACE BLOCK OF THE XRT72L56 FOR MODE 1 (SERIAL/LOOP-TIMED) OPERATION
E3_Clock_In
34.368 MHz Clock Signal
RxOutClk
E3_Data_Out
TxSer
Tx_Start_of_Frame
E3_OH_Ind
TxFrame
TxOH_Ind
NibInt
Terminal Equipment
(Receive Payload Section)
XRT72L5x E3 Framer
Mode 1 Operation of the Terminal Equipment
When the XRT72L56 is operating in this mode it will
function as the source of the 34.368MHz clock signal.
This clock signal will be used as the Terminal Equip-
ment Interface clock by both the XRT72L56 IC and
the Terminal Equipment.
The Terminal Equipment will serially output the pay-
load data of the Outbound E3 data stream via its
E3_Data_Out pin. The Terminal Equipment will up-
date the data on the E3_Data_Out pin upon the rising
edge of the 34.368 MHz clock signal, at its
E3_Clock_In input pin (as depicted in Figures 19 and
20).
The XRT72L56 will latch the Outbound E3 data
stream (from the Terminal Equipment) on the rising
edge of the RxOutClk signal.
The XRT72L56 will indicate that it is processing the
last bit, within a given Outbound E3 frame, by pulsing
its TxFrame output pin “High” for one bit-period.
When the Terminal Equipment detects this pulse at its
Tx_Start_of_Frame input, it is expected to begin
transmission of the very next Outbound E3 frame to
the XRT72L56 via the E3_Data_Out (or TxSer pin).
Finally, the XRT72L56 will indicate that it is about to
process an overhead bit by pulsing the TxOH_Ind
output pin "High" one bit period prior to its processing
of an OH (Overhead) bit. In Figure 157, the
TxOH_Ind output pin is connected to the
E3_Overhead_Ind input pin, of the Terminal Equip-
ment. Whenever the E3_Overhead_Ind pin is pulsed
"High" the Terminal Equipment is expected to not
transmit a E3 payload bit upon the very next clock
edge. Instead, the Terminal Equipment is expected to
delay its transmission of the very next payload bit, by
one clock cycle.
The behavior of the signals, between the XRT72L56
and the Terminal Equipment, for E3 Mode 1 operation
is illustrated in Figure 158.
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