XRT72L56 Datasheet, PDF (74/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
Figure 28 presents a timing diagram which illustrates during a Motorola-type Programmed I/O Write Opera-
the behavior of the Microprocessor Interface signals, tion.
FIGURE 28. ILLUSTRATION OF THE BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNAL, DURING A MOTOROLA-
TYPE PROGRAMMED I/O WRITE OPERATION
ALE_AS
A(11:0)
CS
D(7:0)
RD_DS
WR_R/W
RDY_DTCK
Address of target Register
Data to be Written
2.3.2.2 Data Access using Burst Mode I/O
Burst Mode I/O access is a much faster way to trans-
fer data between the µC/µP and the Microprocessor
Interface (of the XRT72L56 DS3/E3 Framer), than
Programmed I/O. The reason why Burst Mode I/O is
faster is explained below.
Data is placed upon the Address Bus input pins
A[11:0] only for the very first access, within a given
burst access. The remaining read or write operations
(within this burst access) do not require the place-
ment of the Address Data on the Address Data Bus.
As a consequence, the user does not have to wait
through the Address Setup and Hold times for each of
these Read/Write operation, within the Burst Access.
It is important to note that there are some limitations
associated with Burst Mode I/O Operations.
1. All cycles within the Burst Access, must be either
all Read or all Write cycles. No mixing of Read
and Write cycles is permitted.
2. A Burst Access can only be used when Read or
Write operations are to be employed over a con-
tiguous range of address locations, within the
Framer device.
3. The very first Read or Write cycle, within a burst
access, must start at the lowest address value, of
the range of addresses to be accessed. Subse-
quent operations will automatically be incre-
mented to the very next higher address value.
Examples of Burst Mode I/O operations are present-
ed below for read and write operations, with both In-
tel-type and Motorola-type µC/µP.
2.3.2.2.1 Burst I/O Access in the Intel Mode
If the XRT72L56 DS3/E3 Framer is interfaced to an
Intel-type µC/µP (e.g., the 80x86 family, etc.), then it
should be configured to operate in the Intel mode (by
tying the MOTO pin to ground). Intel-type Read and
Write Burst I/O Access operations are described be-
low.
2.3.2.2.1.1 The Intel-Mode Read Burst Access
Whenever an Intel-type µC/µP wishes to read the
contents of numerous registers or buffer locations
over a contiguous range of addresses, then it should
do the following.
a. Perform the initial read operation of the burst
access.
b. Perform the remaining read operations of the
burst access.
c. Terminate the burst access operation.
Each of these operations within the burst access are
described below.
2.3.2.2.1.1.1 The Initial Read Operation
The initial read operation of an Intel-type read burst
access is accomplished by executing a Programmed
I/O Read Cycle as summarized below.
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